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ElbertV2TopModule.par
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Release 14.6 par P.68d (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
ZIREAEL-LAPTOP:: Thu Mar 28 11:26:08 2019
par -filter
C:/Users/ryanh/Dropbox/BRAC/CSE461/Projects/animated_game_stripped/iseconfig/fil
ter.filter -w -intstyle ise -ol high -t 1 ElbertV2TopModule_map.ncd
ElbertV2TopModule.ncd ElbertV2TopModule.pcf
Constraints file: ElbertV2TopModule.pcf.
Loading device for application Rf_Device from file '3s50a.nph' in environment C:\Xilinx\14.6\ISE_DS\ISE\.
"ElbertV2TopModule" is an NCD, version 3.2, device xc3s50a, package tq144, speed -4
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.42 2013-06-08".
Design Summary Report:
Number of External IOBs 38 out of 108 35%
Number of External Input IOBs 15
Number of External Input IBUFs 15
Number of LOCed External Input IBUFs 15 out of 15 100%
Number of External Output IOBs 23
Number of External Output IOBs 23
Number of LOCed External Output IOBs 23 out of 23 100%
Number of External Bidir IOBs 0
Number of BUFGMUXs 4 out of 24 16%
Number of DCMs 1 out of 2 50%
Number of RAMB16BWEs 2 out of 3 66%
Number of Slices 702 out of 704 99%
Number of SLICEMs 26 out of 352 7%
Overall effort level (-ol): High
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 1 secs
Finished initial Timing Analysis. REAL time: 1 secs
WARNING:Par:288 - The signal Switch<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal Switch<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal Switch<5>_IBUF has no load. PAR will not attempt to route this signal.
Starting Placer
Total REAL time at the beginning of Placer: 1 secs
Total CPU time at the beginning of Placer: 1 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:bffe562b) REAL time: 2 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:bffe562b) REAL time: 2 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:bffe562b) REAL time: 2 secs
Phase 4.2 Initial Clock and IO Placement
Phase 4.2 Initial Clock and IO Placement (Checksum:1f41592c) REAL time: 3 secs
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:1f41592c) REAL time: 3 secs
Phase 6.36 Local Placement Optimization
Phase 6.36 Local Placement Optimization (Checksum:1f41592c) REAL time: 3 secs
Phase 7.8 Global Placement
........
..........................................
.............................................
..................
Phase 7.8 Global Placement (Checksum:1e45bb25) REAL time: 4 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:1e45bb25) REAL time: 4 secs
Phase 9.18 Placement Optimization
Phase 9.18 Placement Optimization (Checksum:c80f25f) REAL time: 4 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:c80f25f) REAL time: 4 secs
Total REAL time to Placer completion: 4 secs
Total CPU time to Placer completion: 4 secs
Writing design to file ElbertV2TopModule.ncd
Starting Router
Phase 1 : 4813 unrouted; REAL time: 5 secs
Phase 2 : 4397 unrouted; REAL time: 5 secs
Phase 3 : 1303 unrouted; REAL time: 5 secs
Phase 4 : 1303 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 secs
Updating file: ElbertV2TopModule.ncd with current fully routed design.
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 secs
Total REAL time to Router completion: 7 secs
Total CPU time to Router completion: 7 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| VGA_inst/clock | BUFGMUX_X1Y0| No | 213 | 0.187 | 0.645 |
+---------------------+--------------+------+------+------------+-------------+
| clock | BUFGMUX_X1Y10| No | 65 | 0.123 | 0.590 |
+---------------------+--------------+------+------+------------+-------------+
|SevenSegmentDisplay/ | | | | | |
| clk_i | BUFGMUX_X2Y1| No | 40 | 0.144 | 0.620 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 1
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
PERIOD analysis for net "clocking_inst/CL | SETUP | 1.611ns| 8.388ns| 0| 0
KFX_BUF" derived from NET "clocking_inst | HOLD | 0.998ns| | 0| 0
/CLKIN_IBUFG" PERIOD = 83.3333333 ns HIGH | | | | |
50% | | | | |
----------------------------------------------------------------------------------------------------------
NET "clocking_inst/CLKIN_IBUFG" PERIOD = | MINLOWPULSE | 63.332ns| 20.000ns| 0| 0
83.3333333 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for clocking_inst/CLKIN_IBUFG
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|clocking_inst/CLKIN_IBUFG | 83.333ns| 20.000ns| 69.900ns| 0| 0| 0| 5892|
| clocking_inst/CLKFX_BUF | 10.000ns| 8.388ns| N/A| 0| 0| 5892| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 3 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 7 secs
Total CPU time to PAR completion: 7 secs
Peak Memory Usage: 251 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 5
Number of info messages: 0
Writing design to file ElbertV2TopModule.ncd
PAR done!