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ElbertV2TopModule_map.map
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Release 14.6 Map P.68d (nt)
Xilinx Map Application Log File for Design 'ElbertV2TopModule'
Design Information
------------------
Command Line : map -filter
C:/Users/ryanh/Dropbox/BRAC/CSE461/Projects/animated_game_stripped/iseconfig/fil
ter.filter -intstyle ise -p xc3s50a-tq144-4 -cm area -ir off -pr off -c 100 -o
ElbertV2TopModule_map.ncd ElbertV2TopModule.ngd ElbertV2TopModule.pcf
Target Device : xc3s50a
Target Package : tq144
Target Speed : -4
Mapper Version : spartan3a -- $Revision: 1.55 $
Mapped Date : Thu Mar 28 11:26:02 2019
Mapping design into LUTs...
Running directed packing...
WARNING:Pack:266 - The function generator VGA_inst/output/Mrom_row3_mux000160
failed to merge with F5 multiplexer
VGA_inst/output/Mrom_row3_mux000160_f6/MUXF5.I1. There is a conflict for the
GYMUX. The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator VGA_inst/output/Mrom_row2_mux0001221
failed to merge with F5 multiplexer
VGA_inst/output/Mrom_row2_mux000140_f6/MUXF5.I1. There is a conflict for the
GYMUX. The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator VGA_inst/output/Mrom_row2_mux0001221
failed to merge with F5 multiplexer
VGA_inst/output/Mrom_row2_mux000124_f6/MUXF5.I1. There is a conflict for the
GYMUX. The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator VGA_inst/output/Mrom_row2_mux0001221
failed to merge with F5 multiplexer
VGA_inst/output/Mrom_row2_mux000145_f6/MUXF5.I1. There is a conflict for the
GYMUX. The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator VGA_inst/output/Mrom_row2_mux000128
failed to merge with F5 multiplexer
VGA_inst/output/Mrom_row2_mux000129_f6/MUXF5.I1. There is a conflict for the
GYMUX. The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator VGA_inst/output/Mrom_row2_mux0001221
failed to merge with F5 multiplexer
VGA_inst/output/Mrom_row2_mux000122_f6/MUXF5.I1. There is a conflict for the
GYMUX. The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator VGA_inst/output/Mrom_row3_mux000158
failed to merge with F5 multiplexer
VGA_inst/output/Mrom_row3_mux000158_f6/MUXF5.I1. There is a conflict for the
GYMUX. The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator VGA_inst/output/Mrom_row2_mux0001221
failed to merge with F5 multiplexer
VGA_inst/output/Mrom_row2_mux000141_f6/MUXF5.I1. There is a conflict for the
GYMUX. The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator VGA_inst/output/Mrom_row3_mux000160
failed to merge with F5 multiplexer
VGA_inst/output/Mrom_row3_mux000164_f6/MUXF5.I1. There is a conflict for the
GYMUX. The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator VGA_inst/output/Mrom_row2_mux0001221
failed to merge with F5 multiplexer
VGA_inst/output/Mrom_row2_mux000138_f6/MUXF5.I1. There is a conflict for the
GYMUX. The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator VGA_inst/output/Mrom_row3_mux0001671
failed to merge with F5 multiplexer
VGA_inst/output/Mrom_row3_mux000169_f6/MUXF5.I0. Unable to resolve the
conflicts between two or more collections of symbols which have restrictive
placement or routing requirements. The original symbols are:
MUXF5 symbol "VGA_inst/output/Mrom_row3_mux000169_f6/MUXF5.I0" (Output
Signal = VGA_inst/output/Mrom_row3_mux000169_f6/F5.I0)
LUT symbol "VGA_inst/output/Mrom_row3_mux0001671" (Output Signal =
VGA_inst/output/Mrom_row3_mux0001671)
MUXF5 symbol "VGA_inst/output/Mrom_row3_mux000171_f6/MUXF5.I0" (Output
Signal = VGA_inst/output/Mrom_row3_mux000171_f6/F5.I0)
Failure 1: Unable to combine the following symbols into a single slice.
MUXF5 symbol "VGA_inst/output/Mrom_row3_mux000169_f6/MUXF5.I0" (Output
Signal = VGA_inst/output/Mrom_row3_mux000169_f6/F5.I0)
MUXF5 symbol "VGA_inst/output/Mrom_row3_mux000171_f6/MUXF5.I0" (Output
Signal = VGA_inst/output/Mrom_row3_mux000171_f6/F5.I0)
LUT symbol "VGA_inst/output/Mrom_row3_mux0001671" (Output Signal =
VGA_inst/output/Mrom_row3_mux0001671)
There is more than one F5MUX.
Failure 2: Unable to combine the following symbols into a single slice.
MUXF6 symbol "VGA_inst/output/Mrom_row3_mux000169_f6/MUXF6" (Output Signal =
VGA_inst/output/Mrom_row3_mux000169_f6)
MUXF5 symbol "VGA_inst/output/Mrom_row3_mux000169_f5" (Output Signal =
VGA_inst/output/Mrom_row3_mux000169_f5)
MUXF6 symbol "VGA_inst/output/Mrom_row3_mux000171_f6/MUXF6" (Output Signal =
VGA_inst/output/Mrom_row3_mux000171_f6)
MUXF5 symbol "VGA_inst/output/Mrom_row3_mux000171_f5" (Output Signal =
VGA_inst/output/Mrom_row3_mux000171_f5)
There is more than one MUXF6.
The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator VGA_inst/output/Mrom_row2_mux000128
failed to merge with F5 multiplexer
VGA_inst/output/Mrom_row2_mux000128_f6/MUXF5.I1. There is a conflict for the
GYMUX. The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator VGA_inst/output/Mrom_row3_mux0001671
failed to merge with F5 multiplexer
VGA_inst/output/Mrom_row3_mux000167_f6/MUXF5.I0. Unable to resolve the
conflicts between two or more collections of symbols which have restrictive
placement or routing requirements. The original symbols are:
MUXF5 symbol "VGA_inst/output/Mrom_row3_mux000167_f6/MUXF5.I0" (Output
Signal = VGA_inst/output/Mrom_row3_mux000167_f6/F5.I0)
LUT symbol "VGA_inst/output/Mrom_row3_mux0001671" (Output Signal =
VGA_inst/output/Mrom_row3_mux0001671)
MUXF5 symbol "VGA_inst/output/Mrom_row3_mux000171_f6/MUXF5.I0" (Output
Signal = VGA_inst/output/Mrom_row3_mux000171_f6/F5.I0)
Failure 1: Unable to combine the following symbols into a single slice.
MUXF5 symbol "VGA_inst/output/Mrom_row3_mux000167_f6/MUXF5.I0" (Output
Signal = VGA_inst/output/Mrom_row3_mux000167_f6/F5.I0)
MUXF5 symbol "VGA_inst/output/Mrom_row3_mux000171_f6/MUXF5.I0" (Output
Signal = VGA_inst/output/Mrom_row3_mux000171_f6/F5.I0)
LUT symbol "VGA_inst/output/Mrom_row3_mux0001671" (Output Signal =
VGA_inst/output/Mrom_row3_mux0001671)
There is more than one F5MUX.
Failure 2: Unable to combine the following symbols into a single slice.
MUXF6 symbol "VGA_inst/output/Mrom_row3_mux000167_f6/MUXF6" (Output Signal =
VGA_inst/output/Mrom_row3_mux000167_f6)
MUXF5 symbol "VGA_inst/output/Mrom_row3_mux000167_f5" (Output Signal =
VGA_inst/output/Mrom_row3_mux000167_f5)
MUXF6 symbol "VGA_inst/output/Mrom_row3_mux000171_f6/MUXF6" (Output Signal =
VGA_inst/output/Mrom_row3_mux000171_f6)
MUXF5 symbol "VGA_inst/output/Mrom_row3_mux000171_f5" (Output Signal =
VGA_inst/output/Mrom_row3_mux000171_f5)
There is more than one MUXF6.
The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator VGA_inst/output/Mrom_row3_mux000158
failed to merge with F5 multiplexer
VGA_inst/output/Mrom_row3_mux000159_f6/MUXF5.I1. There is a conflict for the
GYMUX. The design will exhibit suboptimal timing.
Running delay-based LUT packing...
Running related packing...
Running unrelated packing...
Updating timing models...
WARNING:PhysDesignRules:367 - The signal <Switch<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Switch<3>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Switch<5>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:812 - Dangling pin <DIA0> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA1> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA2> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA3> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA4> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA5> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA6> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA7> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA8> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA9> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA10> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA11> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA12> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA13> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA14> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA15> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA16> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA17> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA18> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA19> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA20> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA21> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA22> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA23> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA24> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA25> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA26> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA27> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA28> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA29> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA30> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA31> on
block:<VGA_inst/output/Mrom_row_mux00011>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA0> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA1> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA2> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA3> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA4> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA5> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA6> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA7> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA8> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA9> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA10> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
WARNING:PhysDesignRules:812 - Dangling pin <DIA11> on
block:<VGA_inst/output/Mrom_row_mux00012>:<RAMB16BWE_RAMB16BWE>.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 61
Logic Utilization:
Number of Slice Flip Flops: 466 out of 1,408 33%
Number of 4 input LUTs: 1,128 out of 1,408 80%
Logic Distribution:
Number of occupied Slices: 702 out of 704 99%
Number of Slices containing only related logic: 702 out of 702 100%
Number of Slices containing unrelated logic: 0 out of 702 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 1,341 out of 1,408 95%
Number used as logic: 1,128
Number used as a route-thru: 213
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs: 38 out of 108 35%
Number of BUFGMUXs: 4 out of 24 16%
Number of DCMs: 1 out of 2 50%
Number of RAMB16BWEs: 2 out of 3 66%
Average Fanout of Non-Clock Nets: 3.30
Peak Memory Usage: 241 MB
Total REAL time to MAP completion: 3 secs
Total CPU time to MAP completion: 3 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Mapping completed.
See MAP report file "ElbertV2TopModule_map.mrp" for details.