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animated_game_stripped.gise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="animated_game_stripped.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="ElbertV2TopModule.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="ElbertV2TopModule.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="ElbertV2TopModule.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="ElbertV2TopModule.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="ElbertV2TopModule.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="ElbertV2TopModule.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="ElbertV2TopModule.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="ElbertV2TopModule.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="ElbertV2TopModule.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="ElbertV2TopModule.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ElbertV2TopModule.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="ElbertV2TopModule.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="ElbertV2TopModule.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="ElbertV2TopModule.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="ElbertV2TopModule.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="ElbertV2TopModule.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="ElbertV2TopModule.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="ElbertV2TopModule.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="ElbertV2TopModule.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="ElbertV2TopModule.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="ElbertV2TopModule_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="ElbertV2TopModule_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="ElbertV2TopModule_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="ElbertV2TopModule_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="ElbertV2TopModule_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="ElbertV2TopModule_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="ElbertV2TopModule_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="ElbertV2TopModule_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="ElbertV2TopModule_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="ElbertV2TopModule_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="ElbertV2TopModule_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="ElbertV2TopModule_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="ElbertV2TopModule_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="ElbertV2TopModule_usage.xml"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ElbertV2TopModule_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="ElbertV2TopModule_xst.xrpt"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="clocking.vhd"/>
<file xil_pn:fileType="FILE_UCF" xil_pn:name="clocking_arwz.ucf" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="elbertv2topmodule.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_BIN" xil_pn:name="elbertv2topmodule.bin"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="elbertv2topmodule.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="elbertv2topmodule.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="xaw2vhdl.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1553750738" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1553750738">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1553750738" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4478857063319978070" xil_pn:start_ts="1553750738">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1553750738" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="6299636242150250382" xil_pn:start_ts="1553750738">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1553750738" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1553750738">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1553750738" xil_pn:in_ck="-3677680952026809095" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="5949298753463623042" xil_pn:start_ts="1553750738">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="clocking.vhd"/>
</transform>
<transform xil_pn:end_ts="1553750738" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="1430049303116325842" xil_pn:start_ts="1553750738">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1553750738" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-2198055956500125672" xil_pn:start_ts="1553750738">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1553750755" xil_pn:in_ck="4287821937451974972" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-3478203848695249163" xil_pn:start_ts="1553750738">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="ElbertV2TopModule.lso"/>
<outfile xil_pn:name="ElbertV2TopModule.ngc"/>
<outfile xil_pn:name="ElbertV2TopModule.ngr"/>
<outfile xil_pn:name="ElbertV2TopModule.prj"/>
<outfile xil_pn:name="ElbertV2TopModule.stx"/>
<outfile xil_pn:name="ElbertV2TopModule.syr"/>
<outfile xil_pn:name="ElbertV2TopModule.xst"/>
<outfile xil_pn:name="ElbertV2TopModule_vhdl.prj"/>
<outfile xil_pn:name="ElbertV2TopModule_xst.xrpt"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1553750755" xil_pn:in_ck="7364870414522469439" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-5439097134600962185" xil_pn:start_ts="1553750755">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1553750761" xil_pn:in_ck="-7418122914474591580" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-4605613090057010139" xil_pn:start_ts="1553750755">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ElbertV2TopModule.bld"/>
<outfile xil_pn:name="ElbertV2TopModule.ngd"/>
<outfile xil_pn:name="ElbertV2TopModule_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1553750767" xil_pn:in_ck="7203292064021765285" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="1761500947287708787" xil_pn:start_ts="1553750761">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="ElbertV2TopModule.pcf"/>
<outfile xil_pn:name="ElbertV2TopModule_map.map"/>
<outfile xil_pn:name="ElbertV2TopModule_map.mrp"/>
<outfile xil_pn:name="ElbertV2TopModule_map.ncd"/>
<outfile xil_pn:name="ElbertV2TopModule_map.ngm"/>
<outfile xil_pn:name="ElbertV2TopModule_map.xrpt"/>
<outfile xil_pn:name="ElbertV2TopModule_summary.xml"/>
<outfile xil_pn:name="ElbertV2TopModule_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1553750782" xil_pn:in_ck="-8456982592216891202" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="4891759239423368658" xil_pn:start_ts="1553750767">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ElbertV2TopModule.ncd"/>
<outfile xil_pn:name="ElbertV2TopModule.pad"/>
<outfile xil_pn:name="ElbertV2TopModule.par"/>
<outfile xil_pn:name="ElbertV2TopModule.ptwx"/>
<outfile xil_pn:name="ElbertV2TopModule.unroutes"/>
<outfile xil_pn:name="ElbertV2TopModule.xpi"/>
<outfile xil_pn:name="ElbertV2TopModule_pad.csv"/>
<outfile xil_pn:name="ElbertV2TopModule_pad.txt"/>
<outfile xil_pn:name="ElbertV2TopModule_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1553750793" xil_pn:in_ck="-7545783079291649054" xil_pn:name="TRANEXT_bitFile_spartan3a" xil_pn:prop_ck="-3393961237746444892" xil_pn:start_ts="1553750782">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ElbertV2TopModule.ut"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="elbertv2topmodule.bgn"/>
<outfile xil_pn:name="elbertv2topmodule.bin"/>
<outfile xil_pn:name="elbertv2topmodule.bit"/>
<outfile xil_pn:name="elbertv2topmodule.drc"/>
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1553750782" xil_pn:in_ck="-4362101431703972831" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1553750778">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ElbertV2TopModule.twr"/>
<outfile xil_pn:name="ElbertV2TopModule.twx"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
</transform>
</transforms>
</generated_project>