From 4bc05682d2edaee4f42e4bd4226c273bcdd6c570 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 2 Dec 2022 14:03:54 -0800 Subject: [PATCH 01/16] Fix typos and copy paste error --- .../ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd index 7b0557a7b3..2ac6165fe3 100644 --- a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd @@ -438,8 +438,8 @@ begin dRst => adcBitRst, dClkDiv4 => adcBitClkDiv4, dRstDiv4 => adcBitRstDiv4, - sDataP => adcSerial.fClkP, - sDataN => adcSerial.fClkN, + sDataP => adcSerial.chP(ch), + sDataN => adcSerial.chN(ch), loadDelay => dlyLoad, delay => dlyCfg, bitSlip => bitSlip, @@ -487,7 +487,7 @@ begin begin v := adcR; - v.errorDet := toSl(adcFrame /= "11110000"); + v.errorDet := toSl(adcFrame /= "11111110000000"); adcRin <= v; From 80ccbadf010c8309f66335cf2c4b3f004e655e8d Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 27 Jul 2023 15:49:08 -0700 Subject: [PATCH 02/16] Fix bit order in ultrascale Ad9249Deserializer --- .../ad9249/UltraScale/rtl/Ad9249Deserializer.vhd | 16 ++++++---------- .../ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd | 6 ++---- 2 files changed, 8 insertions(+), 14 deletions(-) diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd index 06d05de1ba..0ef91618a0 100644 --- a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd @@ -207,13 +207,12 @@ begin RST => dRstDiv4 -- 1-bit input: Asynchronous Reset ); - - U_Gearbox : entity surf.Gearbox generic map ( - TPD_G => TPD_G, - SLAVE_WIDTH_G => 8, - MASTER_WIDTH_G => 14 + TPD_G => TPD_G, + SLAVE_WIDTH_G => 8, + MASTER_WIDTH_G => 14, + MASTER_BIT_REVERSE_G => true ) port map ( clk => dClkDiv4, @@ -224,11 +223,8 @@ begin slaveData => masterData, -- Master Interface masterValid => adcValid, - masterData => iAdcData, - masterReady => '1' - ); - - adcData <= iAdcData when BIT_REV_G = '0' else bitReverse(iAdcData(6 downto 0)) & bitReverse(iAdcData(13 downto 7)); + masterData => adcData, + masterReady => '1'); end rtl; diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd index 00c8a00db6..d372835cca 100644 --- a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd @@ -388,8 +388,7 @@ begin IDELAY_CASCADE_G => F_DELAY_CASCADE_G, IDELAYCTRL_FREQ_G => 350.0, DEFAULT_DELAY_G => (others => '0'), - ADC_INVERT_CH_G => '1', - BIT_REV_G => '0') + ADC_INVERT_CH_G => '1') port map ( dClk => adcBitClk, -- Data clock dRst => adcBitRst, @@ -437,8 +436,7 @@ begin IDELAY_CASCADE_G => D_DELAY_CASCADE_G, IDELAYCTRL_FREQ_G => 350.0, DEFAULT_DELAY_G => (others => '0'), - ADC_INVERT_CH_G => ADC_INVERT_CH_G(i), - BIT_REV_G => '1') + ADC_INVERT_CH_G => ADC_INVERT_CH_G(i)) port map ( dClk => adcBitClk, -- Data clock dRst => adcBitRst, From 0f3e3e9b7faf086431c8c29681fefcf10ee72f12 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 27 Jul 2023 15:51:54 -0700 Subject: [PATCH 03/16] Always synthsize 8 channels on AXIL bus for software compatibility --- .../ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd index 2ac6165fe3..bcb46bb186 100644 --- a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd @@ -74,8 +74,8 @@ architecture rtl of Ad9249ReadoutGroup2 is delay : slv(8 downto 0); delaySet : sl; freezeDebug : sl; - readoutDebug0 : slv16Array(NUM_CHANNELS_G-1 downto 0); - readoutDebug1 : slv16Array(NUM_CHANNELS_G-1 downto 0); + readoutDebug0 : slv16Array(7 downto 0); + readoutDebug1 : slv16Array(7 downto 0); lockedCountRst : sl; invert : sl; realign : sl; @@ -136,7 +136,7 @@ architecture rtl of Ad9249ReadoutGroup2 is signal debugDataValid : sl; signal debugDataOut : slv(NUM_CHANNELS_G*16-1 downto 0); - signal debugDataTmp : slv16Array(NUM_CHANNELS_G-1 downto 0); + signal debugDataTmp : slv16Array(7 downto 0); signal invertSync : sl; signal bitSlip : sl; @@ -322,7 +322,7 @@ begin axiSlaveRegister(axilEp, X"60", 0, v.invert); -- Debug registers. Output the last 2 words received - for ch in 0 to NUM_CHANNELS_G-1 loop + for ch in 0 to 7 loop axiSlaveRegisterR(axilEp, X"80"+toSlv((ch*4), 8), 0, axilR.readoutDebug0(ch)); axiSlaveRegisterR(axilEp, X"80"+toSlv((ch*4), 8), 16, axilR.readoutDebug1(ch)); end loop; From 5faa9a9b286885a4e3bf7af2438a0a1d21555357 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 27 Jul 2023 15:52:58 -0700 Subject: [PATCH 04/16] Many bug fixes found in simulation --- .../UltraScale/rtl/Ad9249ReadoutGroup2.vhd | 70 ++++++++++--------- 1 file changed, 38 insertions(+), 32 deletions(-) diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd index bcb46bb186..2a6898d7dd 100644 --- a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd @@ -92,7 +92,7 @@ architecture rtl of Ad9249ReadoutGroup2 is readoutDebug1 => (others => (others => '0')), lockedCountRst => '0', invert => '0', - realign => '0', + realign => '1', minEyeWidth => X"50"); signal lockedSync : sl; @@ -109,7 +109,7 @@ architecture rtl of Ad9249ReadoutGroup2 is end record; constant ADC_REG_INIT_C : AdcRegType := ( - errorDet => '0'); + errorDet => '1'); signal adcR : AdcRegType := ADC_REG_INIT_C; @@ -122,11 +122,12 @@ architecture rtl of Ad9249ReadoutGroup2 is signal adcBitClkDiv4 : sl; signal adcBitRstDiv4 : sl; - signal adcFrame : slv(13 downto 0); - signal adcFrameValid : sl; - signal adcFrameSync : slv(13 downto 0); - signal adcData : slv14Array(NUM_CHANNELS_G-1 downto 0); - signal adcDataValid : slv(NUM_CHANNELS_G-1 downto 0); + signal adcFrame : slv(13 downto 0); + signal adcFrameValid : sl; + signal adcFrameSync : slv(13 downto 0); + signal adcFrameSyncValid : sl; + signal adcData : slv14Array(NUM_CHANNELS_G-1 downto 0); + signal adcDataValid : slv(NUM_CHANNELS_G-1 downto 0); signal fifoWrData : slv16Array(NUM_CHANNELS_G-1 downto 0); signal fifoDataValid : sl; @@ -204,16 +205,21 @@ begin rdRst => axilRst); - SynchronizerVector_FRAME : entity surf.SynchronizerVector + SynchronizerVector_FRAME : entity surf.SynchronizerFifo generic map ( - TPD_G => TPD_G, - STAGES_G => 2, - WIDTH_G => 14) + TPD_G => TPD_G, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 14, + ADDR_WIDTH_G => 4) port map ( - clk => axilClk, - rst => axilRst, - dataIn => adcFrame, - dataOut => adcFrameSync); + rst => axilRst, + wr_clk => adcBitClkDiv4, + wr_en => adcFrameValid, + din => adcFrame, + rd_clk => axilClk, + rd_en => adcFrameSyncValid, + valid => adcFrameSyncValid, + dout => adcFrameSync); U_SynchronizerVector_CUR_DELAY : entity surf.SynchronizerVector generic map ( @@ -237,15 +243,14 @@ begin dataIn => axilR.invert, dataOut => invertSync); - Synchronizer_REALIGN : entity surf.SynchronizerEdge + Synchronizer_REALIGN : entity surf.RstSync generic map ( - TPD_G => TPD_G, - STAGES_G => 3) + TPD_G => TPD_G, + RELEASE_DELAY_G => 3) port map ( - clk => adcBitClkDiv4, - rst => adcBitRstDiv4, - dataIn => axilR.realign, - risingEdge => realignSync); + clk => adcBitClkDiv4, + asyncRst => axilR.realign, + syncRst => realignSync); Synchronizer_USR_DELAY_SET : entity surf.Synchronizer generic map ( @@ -308,6 +313,7 @@ begin axiWrDetect(axilEp, X"00", v.delaySet); axiSlaveRegisterR(axilEp, X"00", 0, curDelay); + v.realign := '0'; axiSlaveRegister(axilEp, X"20", 0, v.realign); axiSlaveRegisterR(axilEp, X"30", 0, errorDetCount); @@ -404,13 +410,12 @@ begin SIM_DEVICE_G => SIM_DEVICE_G, DEFAULT_DELAY_G => DEFAULT_DELAY_G, IDELAYCTRL_FREQ_G => 350.0, -- Check this - ADC_INVERT_CH_G => '0', -- Should maybe be '1' - BIT_REV_G => '0') + ADC_INVERT_CH_G => '0') port map ( dClk => adcBitClk, dRst => adcBitRst, dClkDiv4 => adcBitClkDiv4, - dRstDiv4 => adcBitRstDiv4, + dRstDiv4 => realignSync, sDataP => adcSerial.fClkP, sDataN => adcSerial.fClkN, loadDelay => dlyLoad, @@ -431,13 +436,12 @@ begin SIM_DEVICE_G => SIM_DEVICE_G, DEFAULT_DELAY_G => DEFAULT_DELAY_G, IDELAYCTRL_FREQ_G => 350.0, -- Check this - ADC_INVERT_CH_G => ADC_INVERT_CH_G(ch), -- Should maybe be '1' - BIT_REV_G => '1') + ADC_INVERT_CH_G => ADC_INVERT_CH_G(ch)) -- Should maybe be '1' port map ( dClk => adcBitClk, dRst => adcBitRst, dClkDiv4 => adcBitClkDiv4, - dRstDiv4 => adcBitRstDiv4, + dRstDiv4 => realignSync, sDataP => adcSerial.chP(ch), sDataN => adcSerial.chN(ch), loadDelay => dlyLoad, @@ -482,12 +486,14 @@ begin ------------------------------------------------------------------------------------------------- -- ADC Bit Clocked Logic ------------------------------------------------------------------------------------------------- - adcComb : process (adcFrame, adcR) is + adcComb : process (adcFrame, adcFrameValid, adcR) is variable v : AdcRegType; begin v := adcR; - v.errorDet := toSl(adcFrame /= "11111110000000"); + if (adcFrameValid = '1') then + v.errorDet := toSl(adcFrame /= "11111110000000"); + end if; adcRin <= v; @@ -545,7 +551,7 @@ begin port map ( rst => adcBitRstDiv4, wr_clk => adcBitClkDiv4, - wr_en => '1', --Always write data + wr_en => adcFrameValid, --Always write data din => fifoDataIn, rd_clk => adcStreamClk, rd_en => fifoDataValid, @@ -562,7 +568,7 @@ begin port map ( rst => adcBitRstDiv4, wr_clk => adcBitClkDiv4, - wr_en => '1', --Always write data + wr_en => adcFrameValid, --Always write data din => fifoDataIn, rd_clk => axilClk, rd_en => debugDataValid, From dd5810f9420aec3b342b4be555d16b3b9d26458a Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 27 Jul 2023 15:55:20 -0700 Subject: [PATCH 05/16] Fix AD9249 simulation clocking Always load 7Series clock manager needed by module --- .../AnalogDevices/ad9249/tb/Ad9249Group.vhd | 55 ++++++++++--------- devices/AnalogDevices/ruckus.tcl | 6 +- 2 files changed, 33 insertions(+), 28 deletions(-) diff --git a/devices/AnalogDevices/ad9249/tb/Ad9249Group.vhd b/devices/AnalogDevices/ad9249/tb/Ad9249Group.vhd index 694c68637f..02db1c9676 100644 --- a/devices/AnalogDevices/ad9249/tb/Ad9249Group.vhd +++ b/devices/AnalogDevices/ad9249/tb/Ad9249Group.vhd @@ -32,8 +32,8 @@ entity Ad9249Group is CLK_PERIOD_G : time := 24 ns; DIVCLK_DIVIDE_G : integer := 1; CLKFBOUT_MULT_G : integer := 49; - CLK_DCO_DIVIDE_G : integer := 49; - CLK_FCO_DIVIDE_G : integer := 7); + CLK_DCO_DIVIDE_G : integer := 7; + CLK_FCO_DIVIDE_G : integer := 49); port ( clk : in sl; @@ -230,31 +230,32 @@ begin -- Use a clock manager to create the serial clock -- There's probably a better way but this works. ------------------------------------------------------------------------------------------------- - U_CtrlClockManager7 : entity surf.ClockManager7 - generic map ( - TPD_G => TPD_G, - TYPE_G => "MMCM", - INPUT_BUFG_G => false, - FB_BUFG_G => true, - NUM_CLOCKS_G => 4, - BANDWIDTH_G => "HIGH", - CLKIN_PERIOD_G => CLK_PERIOD_C, - DIVCLK_DIVIDE_G => DIVCLK_DIVIDE_G, - CLKFBOUT_MULT_G => CLKFBOUT_MULT_G, - CLKOUT0_DIVIDE_G => CLK_FCO_DIVIDE_G, - CLKOUT1_DIVIDE_G => CLK_DCO_DIVIDE_G, - CLKOUT2_DIVIDE_G => CLK_DCO_DIVIDE_G, - CLKOUT2_PHASE_G => 90.0, - CLKOUT3_DIVIDE_G => CLK_FCO_DIVIDE_G, - CLKOUT3_PHASE_G => 257.143) - port map ( - clkIn => clk, - rstIn => pllRst, - clkOut(0) => fClk, - clkOut(1) => dClk, - clkOut(2) => dco, - clkOut(3) => fco, - locked => locked); + U_CtrlClockManager7 : entity surf.ClockManager7 + generic map ( + TPD_G => TPD_G, + TYPE_G => "PLL", + INPUT_BUFG_G => false, + FB_BUFG_G => true, + NUM_CLOCKS_G => 4, + BANDWIDTH_G => "HIGH", + CLKIN_PERIOD_G => CLK_PERIOD_C, + DIVCLK_DIVIDE_G => DIVCLK_DIVIDE_G, + CLKFBOUT_MULT_G => CLKFBOUT_MULT_G, + CLKOUT0_DIVIDE_G => CLK_FCO_DIVIDE_G, + CLKOUT1_DIVIDE_G => CLK_DCO_DIVIDE_G, + CLKOUT2_DIVIDE_G => CLK_DCO_DIVIDE_G, + CLKOUT2_PHASE_G => 90.0, + CLKOUT3_DIVIDE_G => CLK_FCO_DIVIDE_G, + CLKOUT3_PHASE_G => 257.143) + port map ( + clkIn => clk, + rstIn => pllRst, + clkOut(0) => fClk, + clkOut(1) => dClk, + clkOut(2) => dco, + clkOut(3) => fco, + locked => locked); + RstSync_1 : entity surf.RstSync diff --git a/devices/AnalogDevices/ruckus.tcl b/devices/AnalogDevices/ruckus.tcl index 26eff96e1a..c39c9f5ad3 100644 --- a/devices/AnalogDevices/ruckus.tcl +++ b/devices/AnalogDevices/ruckus.tcl @@ -10,4 +10,8 @@ if { $::env(VIVADO_VERSION) > 0.0} { loadRuckusTcl "$::DIR_PATH/ad9467" loadRuckusTcl "$::DIR_PATH/ad9249" loadRuckusTcl "$::DIR_PATH/ad9681" -} \ No newline at end of file + + # AD9249 sim model requires ClockManager7 + loadSource -lib surf -path "$::DIR_PATH/../../xilinx/7Series/general/rtl/ClockManager7.vhd" + loadSource -lib surf -path "$::DIR_PATH/../../xilinx/7Series/general/rtl/ClockManager7Pkg.vhd" +} From dac77afe39c444acd654e8fd0b040cea243bde8b Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 27 Jul 2023 15:55:41 -0700 Subject: [PATCH 06/16] Add rogue Device for Ad9249ReadoutGroup2 --- python/surf/devices/analog_devices/_Ad9249.py | 151 ++++++++++++++++++ 1 file changed, 151 insertions(+) diff --git a/python/surf/devices/analog_devices/_Ad9249.py b/python/surf/devices/analog_devices/_Ad9249.py index f497266b13..01a19330d5 100644 --- a/python/surf/devices/analog_devices/_Ad9249.py +++ b/python/surf/devices/analog_devices/_Ad9249.py @@ -421,6 +421,157 @@ def readBlocks(self, *, recurse=True, variable=None, checkEach=False, index=-1, for key,value in self.devices.items(): value.readBlocks(recurse=True, checkEach=checkEach, **kwargs) + +class Ad9249ReadoutGroup2(pr.Device): + def __init__(self, + name = 'Ad9249Readout', + description = 'Configure readout of 1 bank of an AD9249', + fpga = '7series', + channels = 8, + **kwargs): + + assert (channels > 0 and channels <= 8), f'channels ({channels}) must be between 0 and 8' + super().__init__(name=name, description=description, **kwargs) + + if fpga == '7series': + delayBits = 6 + elif fpga == 'ultrascale': + delayBits = 9 + else: + delayBits = 6 + + + self.add(pr.RemoteVariable( + name = f'Delay', + description = f'IDELAY value', + offset = 0x00, + bitSize = delayBits, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + verify = False, + )) + + self.add(pr.RemoteCommand( + name='Relock', + hidden=False, + offset=0x20, + bitSize=1, + bitOffset=0, + base=pr.UInt, + function=pr.RemoteCommand.toggle)) + + self.add(pr.RemoteVariable( + name = f'ErrorDetCount', + description = 'Number of times that frame lock has been lost since reset', + offset = 0x30, + disp = '{:d}', + bitSize = 16, + bitOffset = 0, + base = pr.UInt, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = f'LostLockCount', + description = 'Number of times that frame lock has been lost since reset', + offset = 0x50, + bitSize = 16, + bitOffset = 0, + base = pr.UInt, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = f'Locked', + description = 'Readout has locked on to the frame boundary', + offset = 0x50, + bitSize = 1, + bitOffset = 16, + base = pr.Bool, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = f'AdcFrameSync', + description = 'Last deserialized FCO value for debug', + offset = 0x58, + bitSize = 14, + base = pr.UInt, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'Invert', + description = 'Optional ADC data inversion (offset binary only)', + offset = 0x60, + bitSize = 1, + bitOffset = 0, + base = pr.Bool, + mode = 'RW', + )) + + for i in range(channels): + self.add(pr.RemoteVariable( + name = f'AdcChannel[{i:d}]', + description = f'Last deserialized channel {i:d} ADC value for debug', + offset = 0x80 + (i*4), + bitSize = 32, + bitOffset = 0, + base = pr.UInt, + disp = '{:09_x}', + mode = 'RO', + )) + + for i in range(channels): + self.add(pr.LinkVariable( + name = f'AdcVoltage[{i}]', + mode = 'RO', + disp = '{:1.9f}', + variable = self.AdcChannel[i], + linkedGet = lambda read, check, r=self.AdcChannel[i]: 2*pr.twosComplement(r.get(read=read, check=check)>>18, 14)/2**14, + units = 'V')) + + self.add(pr.RemoteCommand( + name = 'LostLockCountReset', + description = 'Reset LostLockCount', + function = pr.BaseCommand.toggle, + offset = 0x5C, + bitSize = 1, + bitOffset = 0, + )) + + self.add(pr.RemoteCommand( + name='FreezeDebug', + description='Freeze all of the AdcChannel registers', + hidden=True, + offset=0xA0, + bitSize=1, + bitOffset=0, + base=pr.UInt, + function=pr.RemoteCommand.touch)) + + def readBlocks(self, *, recurse=True, variable=None, checkEach=False, index=-1, **kwargs): + """ + Perform background reads + """ + checkEach = checkEach or self.forceCheckEach + + if variable is not None: + pr.startTransaction(variable._block, type=rim.Read, checkEach=checkEach, variable=variable, index=index, **kwargs) + + else: + self.FreezeDebug(1) + for block in self._blocks: + if block.bulkOpEn: + pr.startTransaction(block, type=rim.Read, checkEach=checkEach, **kwargs) + self.FreezeDebug(0) + + if recurse: + for key,value in self.devices.items(): + value.readBlocks(recurse=True, checkEach=checkEach, **kwargs) + + class AdcTester(pr.Device): def __init__(self, **kwargs): """Create AdcTester""" From 7543f43e19f8ece707383f5e3d5f77136836578b Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 27 Jul 2023 16:00:59 -0700 Subject: [PATCH 07/16] Remove unused generic --- .../AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd index 1211099993..a6b8d5c045 100644 --- a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd @@ -38,8 +38,7 @@ entity Ad9249Deserializer is IDELAY_CASCADE_G : boolean := false; IDELAYCTRL_FREQ_G : real := 300.0; DEFAULT_DELAY_G : slv(8 downto 0) := (others => '0'); - ADC_INVERT_CH_G : sl := '0'; - BIT_REV_G : sl := '0'); + ADC_INVERT_CH_G : sl := '0'); port ( -- Serial Data from ADC dClk : in sl; -- Data clock From 1c37efec746a8bcccf250af7ab911ac28344de85 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 3 Aug 2023 14:20:31 -0700 Subject: [PATCH 08/16] Add NoConfig option for some variables --- python/surf/devices/analog_devices/_Ad9249.py | 1 + 1 file changed, 1 insertion(+) diff --git a/python/surf/devices/analog_devices/_Ad9249.py b/python/surf/devices/analog_devices/_Ad9249.py index 01a19330d5..2e978e5834 100644 --- a/python/surf/devices/analog_devices/_Ad9249.py +++ b/python/surf/devices/analog_devices/_Ad9249.py @@ -450,6 +450,7 @@ def __init__(self, base = pr.UInt, mode = 'RW', verify = False, + groups = 'NoConfig', )) self.add(pr.RemoteCommand( From 420e2076cfc98aee4028c91ccce4a0f4d88915b6 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 15 Sep 2023 10:08:06 -0700 Subject: [PATCH 09/16] Use larger step size in simulation for faster lock --- .../AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd index 2a6898d7dd..0a4a261023 100644 --- a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd @@ -461,7 +461,7 @@ begin TPD_G => TPD_G, SIMULATION_G => SIMULATION_G, CODE_TYPE_G => "LINE_CODE", - DLY_STEP_SIZE_G => 1) + DLY_STEP_SIZE_G => ite(SIMULATION_G, 16, 1)) port map ( clk => adcBitClkDiv4, -- [in] rst => adcBitRstDiv4, -- [in] From 92d70938e6f97780fdf5742fa0f7db4373276f23 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 13 Nov 2023 13:27:14 -0800 Subject: [PATCH 10/16] Linting --- python/surf/devices/analog_devices/_Ad9249.py | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/python/surf/devices/analog_devices/_Ad9249.py b/python/surf/devices/analog_devices/_Ad9249.py index 2e978e5834..a25c07934c 100644 --- a/python/surf/devices/analog_devices/_Ad9249.py +++ b/python/surf/devices/analog_devices/_Ad9249.py @@ -442,8 +442,8 @@ def __init__(self, self.add(pr.RemoteVariable( - name = f'Delay', - description = f'IDELAY value', + name = 'Delay', + description = 'IDELAY value', offset = 0x00, bitSize = delayBits, bitOffset = 0, @@ -452,7 +452,7 @@ def __init__(self, verify = False, groups = 'NoConfig', )) - + self.add(pr.RemoteCommand( name='Relock', hidden=False, @@ -461,9 +461,9 @@ def __init__(self, bitOffset=0, base=pr.UInt, function=pr.RemoteCommand.toggle)) - + self.add(pr.RemoteVariable( - name = f'ErrorDetCount', + name = 'ErrorDetCount', description = 'Number of times that frame lock has been lost since reset', offset = 0x30, disp = '{:d}', @@ -474,7 +474,7 @@ def __init__(self, )) self.add(pr.RemoteVariable( - name = f'LostLockCount', + name = 'LostLockCount', description = 'Number of times that frame lock has been lost since reset', offset = 0x50, bitSize = 16, @@ -484,7 +484,7 @@ def __init__(self, )) self.add(pr.RemoteVariable( - name = f'Locked', + name = 'Locked', description = 'Readout has locked on to the frame boundary', offset = 0x50, bitSize = 1, @@ -494,7 +494,7 @@ def __init__(self, )) self.add(pr.RemoteVariable( - name = f'AdcFrameSync', + name = 'AdcFrameSync', description = 'Last deserialized FCO value for debug', offset = 0x58, bitSize = 14, From fb8aa2cc330941954c95335614d87f0e770faf7f Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 18 Dec 2023 13:42:04 -0800 Subject: [PATCH 11/16] Update LICENSE.txt --- LICENSE.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/LICENSE.txt b/LICENSE.txt index 44e3f12dca..9aa129c6fb 100644 --- a/LICENSE.txt +++ b/LICENSE.txt @@ -1,5 +1,5 @@ -Copyright (c) 2023, The Board of Trustees of the Leland Stanford Junior +Copyright (c) 2024, The Board of Trustees of the Leland Stanford Junior University, through SLAC National Accelerator Laboratory (subject to receipt of any required approvals from the U.S. Dept. of Energy). All rights reserved. Redistribution and use in source and binary forms, with or without From b810329d26bd0d9281cb06a9a052ae0369edea37 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 6 Feb 2024 10:41:39 -0800 Subject: [PATCH 12/16] Restore BIT_REV_G functionality --- .../UltraScale/rtl/Ad9249Deserializer.vhd | 5 +- .../UltraScale/rtl/Ad9249ReadoutGroup.vhd | 176 +++++++++--------- 2 files changed, 92 insertions(+), 89 deletions(-) diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd index a6b8d5c045..d8b08f5f12 100644 --- a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd @@ -38,7 +38,8 @@ entity Ad9249Deserializer is IDELAY_CASCADE_G : boolean := false; IDELAYCTRL_FREQ_G : real := 300.0; DEFAULT_DELAY_G : slv(8 downto 0) := (others => '0'); - ADC_INVERT_CH_G : sl := '0'); + ADC_INVERT_CH_G : sl := '0'; + BIT_REV_G : sl := '0'); port ( -- Serial Data from ADC dClk : in sl; -- Data clock @@ -211,7 +212,7 @@ begin TPD_G => TPD_G, SLAVE_WIDTH_G => 8, MASTER_WIDTH_G => 14, - MASTER_BIT_REVERSE_G => true + MASTER_BIT_REVERSE_G => toBoolean(BIT_REV_G) ) port map ( clk => dClkDiv4, diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd index 02343a921e..e610af0cab 100644 --- a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd @@ -45,36 +45,36 @@ entity Ad9249ReadoutGroup is SIM_SPEEDUP_G : boolean := false); port ( -- Master system clock, 125Mhz - axilClk : in sl; - axilRst : in sl; + axilClk : in sl; + axilRst : in sl; -- Axi Interface - axilWriteMaster : in AxiLiteWriteMasterType; - axilWriteSlave : out AxiLiteWriteSlaveType; - axilReadMaster : in AxiLiteReadMasterType; - axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType; + axilWriteSlave : out AxiLiteWriteSlaveType; + axilReadMaster : in AxiLiteReadMasterType; + axilReadSlave : out AxiLiteReadSlaveType; -- Reset for adc deserializer (axilClk domain) - adcClkRst : in sl; + adcClkRst : in sl; -- clocks must be provided with USE_MMCME_G = false -- this option is necessary if there is many ADCs -- one external MMCM should be instantiated to be used with all Ad9249ReadoutGroups - adcBitClkIn : in sl; -- 350.0 MHz - adcBitClkDiv4In : in sl; -- 87.5 MHz - adcBitRstIn : in sl; - adcBitRstDiv4In : in sl; + adcBitClkIn : in sl; -- 350.0 MHz + adcBitClkDiv4In : in sl; -- 87.5 MHz + adcBitRstIn : in sl; + adcBitRstDiv4In : in sl; -- Serial Data from ADC - adcSerial : in Ad9249SerialGroupType; + adcSerial : in Ad9249SerialGroupType; -- Deserialized ADC Data - adcStreamClk : in sl; - adcStreams : out AxiStreamMasterArray(NUM_CHANNELS_G-1 downto 0) := - (others => axiStreamMasterInit((false, 2, 8, 0, TKEEP_NORMAL_C, 0, TUSER_NORMAL_C))); + adcStreamClk : in sl; + adcStreams : out AxiStreamMasterArray(NUM_CHANNELS_G-1 downto 0) := + (others => axiStreamMasterInit((false, 2, 8, 0, TKEEP_NORMAL_C, 0, TUSER_NORMAL_C))); -- optional ready to allow evenout samples readout in adcStreamClk - adcReady : in slv(NUM_CHANNELS_G-1 downto 0) := (others => '1') - ); + adcReady : in slv(NUM_CHANNELS_G-1 downto 0) := (others => '1') + ); end Ad9249ReadoutGroup; -- Define architecture @@ -111,7 +111,7 @@ architecture rtl of Ad9249ReadoutGroup is readoutDebug1 => (others => (others => '0')), lockedCountRst => '0', invert => '0' - ); + ); signal lockedSync : sl; signal lockedFallCount : slv(15 downto 0); @@ -123,24 +123,24 @@ architecture rtl of Ad9249ReadoutGroup is -- ADC Readout Clocked Registers ------------------------------------------------------------------------------------------------- type AdcRegType is record - slip : sl; - count : slv(5 downto 0); + slip : sl; + count : slv(5 downto 0); --loadDelay : sl; --delayValue : slv(8 downto 0); - locked : sl; - fifoWrData : Slv16Array(NUM_CHANNELS_G-1 downto 0); - fifoWrDataEn : slv(NUM_CHANNELS_G-1 downto 0); + locked : sl; + fifoWrData : Slv16Array(NUM_CHANNELS_G-1 downto 0); + fifoWrDataEn : slv(NUM_CHANNELS_G-1 downto 0); end record; constant ADC_REG_INIT_C : AdcRegType := ( - slip => '0', - count => (others => '0'), + slip => '0', + count => (others => '0'), --loadDelay => '0', --delayValue => (others => '0'), - locked => '0', - fifoWrData => (others => (others => '0')), - fifoWrDataEn => (others => '0') - ); + locked => '0', + fifoWrData => (others => (others => '0')), + fifoWrDataEn => (others => '0') + ); signal adcR : AdcRegType := ADC_REG_INIT_C; signal adcRin : AdcRegType; @@ -157,9 +157,9 @@ architecture rtl of Ad9249ReadoutGroup is signal adcBitRst : sl; signal adcClkRstSync : sl; - signal adcFrame : slv(13 downto 0); - signal adcFrameSync : slv(13 downto 0); - signal adcData : Slv14Array(NUM_CHANNELS_G-1 downto 0); + signal adcFrame : slv(13 downto 0); + signal adcFrameSync : slv(13 downto 0); + signal adcData : Slv14Array(NUM_CHANNELS_G-1 downto 0); signal curDelayFrame : slv(8 downto 0); signal curDelayData : slv9Array(NUM_CHANNELS_G-1 downto 0); @@ -173,7 +173,7 @@ architecture rtl of Ad9249ReadoutGroup is signal frameDelay : slv(8 downto 0); signal frameDelaySet : sl; - signal invertSync : sl; + signal invertSync : sl; begin ------------------------------------------------------------------------------------------------- @@ -198,7 +198,7 @@ begin rdClk => axilClk, rdRst => axilRst, cntRst => axilR.lockedCountRst - ); + ); Synchronizer_1 : entity surf.Synchronizer generic map ( @@ -240,9 +240,9 @@ begin begin v := axilR; - v.dataDelaySet := (others => '0'); - v.frameDelaySet := '0'; - v.lockedCountRst := '0'; + v.dataDelaySet := (others => '0'); + v.frameDelaySet := '0'; + v.lockedCountRst := '0'; -- Store last two samples read from ADC for i in 0 to NUM_CHANNELS_G-1 loop @@ -318,14 +318,14 @@ begin G_MMCM : if USE_MMCME_G = true generate AdcClk_I_Ibufds : IBUFDS - generic map ( - DQS_BIAS => "FALSE" - ) - port map ( - I => adcSerial.dClkP, - IB => adcSerial.dClkN, - O => adcDclk - ); + generic map ( + DQS_BIAS => "FALSE" + ) + port map ( + I => adcSerial.dClkP, + IB => adcSerial.dClkN, + O => adcDclk + ); ------------------------------------------ -- Generate clocks from ADC incoming clock @@ -335,22 +335,22 @@ begin -- clkOut(1) : 87.50 MHz adcBitClkDiv4 clock U_iserdesClockGen : entity surf.ClockManagerUltraScale generic map( - TPD_G => 1 ns, - TYPE_G => "MMCM", -- or "PLL" - INPUT_BUFG_G => true, - FB_BUFG_G => true, - RST_IN_POLARITY_G => '1', -- '0' for active low - NUM_CLOCKS_G => 2, + TPD_G => 1 ns, + TYPE_G => "MMCM", -- or "PLL" + INPUT_BUFG_G => true, + FB_BUFG_G => true, + RST_IN_POLARITY_G => '1', -- '0' for active low + NUM_CLOCKS_G => 2, -- MMCM attributes - BANDWIDTH_G => "OPTIMIZED", - CLKIN_PERIOD_G => 2.85, -- Input period in ns ); - DIVCLK_DIVIDE_G => 10, - CLKFBOUT_MULT_F_G => 20.0, - CLKFBOUT_MULT_G => 5, - CLKOUT0_DIVIDE_F_G => 1.0, - CLKOUT0_DIVIDE_G => 2, - CLKOUT1_DIVIDE_G => 8 - ) + BANDWIDTH_G => "OPTIMIZED", + CLKIN_PERIOD_G => 2.85, -- Input period in ns ); + DIVCLK_DIVIDE_G => 10, + CLKFBOUT_MULT_F_G => 20.0, + CLKFBOUT_MULT_G => 5, + CLKOUT0_DIVIDE_F_G => 1.0, + CLKOUT0_DIVIDE_G => 2, + CLKOUT1_DIVIDE_G => 8 + ) port map( clkIn => adcDclk, rstIn => '0', @@ -359,16 +359,16 @@ begin rstOut(0) => adcBitRst, rstOut(1) => adcBitRstDiv4, locked => open - ); + ); end generate G_MMCM; G_NO_MMCM : if USE_MMCME_G = false generate - adcBitClk <= adcBitClkIn; - adcBitClkDiv4 <= adcBitClkDiv4In; - adcBitRst <= adcBitRstIn; - adcBitRstDiv4 <= adcBitRstDiv4In; + adcBitClk <= adcBitClkIn; + adcBitClkDiv4 <= adcBitClkDiv4In; + adcBitRst <= adcBitRstIn; + adcBitRstDiv4 <= adcBitRstDiv4In; end generate G_NO_MMCM; @@ -383,9 +383,10 @@ begin IDELAY_CASCADE_G => F_DELAY_CASCADE_G, IDELAYCTRL_FREQ_G => 350.0, DEFAULT_DELAY_G => (others => '0'), - ADC_INVERT_CH_G => '1') + ADC_INVERT_CH_G => '1', + BIT_REV_G => '0') port map ( - dClk => adcBitClk, -- Data clock + dClk => adcBitClk, -- Data clock dRst => adcBitRst, dClkDiv4 => adcBitClkDiv4, dRstDiv4 => adcBitRstDiv4, @@ -397,7 +398,7 @@ begin bitSlip => adcR.slip, adcData => adcFrame, adcValid => adcFrameValid - ); + ); U_FrmDlyFifo : entity surf.SynchronizerFifo generic map ( @@ -432,9 +433,10 @@ begin IDELAY_CASCADE_G => D_DELAY_CASCADE_G, IDELAYCTRL_FREQ_G => 350.0, DEFAULT_DELAY_G => (others => '0'), - ADC_INVERT_CH_G => ADC_INVERT_CH_G(i)) + ADC_INVERT_CH_G => ADC_INVERT_CH_G(i), + BIT_REV_G => '1') port map ( - dClk => adcBitClk, -- Data clock + dClk => adcBitClk, -- Data clock dRst => adcBitRst, dClkDiv4 => adcBitClkDiv4, dRstDiv4 => adcBitRstDiv4, @@ -479,7 +481,7 @@ begin ---------------------------------------------------------------------------------------------- -- Slip bits until correct alignment seen ---------------------------------------------------------------------------------------------- - v.slip := '0'; + v.slip := '0'; if (adcR.count = 0) then if adcFrameValid = '1' then if (adcFrame = FRAME_PATTERN_C) then @@ -535,14 +537,14 @@ begin end process adcSeq; RstSync_1 : entity surf.RstSync - generic map ( - TPD_G => TPD_G - ) - port map ( - clk => adcBitClkDiv4, - asyncRst => adcClkRst, - syncRst => adcClkRstSync - ); + generic map ( + TPD_G => TPD_G + ) + port map ( + clk => adcBitClkDiv4, + asyncRst => adcClkRst, + syncRst => adcClkRstSync + ); -- synchronize data cross-clocks G_FIFO_SYNC : for i in NUM_CHANNELS_G-1 downto 0 generate @@ -550,9 +552,9 @@ begin U_DataFifo : entity surf.SynchronizerFifo generic map ( - TPD_G => TPD_G, - DATA_WIDTH_G => 16, - ADDR_WIDTH_G => 4) + TPD_G => TPD_G, + DATA_WIDTH_G => 16, + ADDR_WIDTH_G => 4) port map ( rst => adcBitRstDiv4, wr_clk => adcBitClkDiv4, @@ -562,7 +564,7 @@ begin rd_en => fifoDataRdEn(i), valid => fifoDataValid(i), dout => adcStreams(i).tdata(15 downto 0) - ); + ); fifoDataRdEn(i) <= adcReady(i) and fifoDataValid(i); adcStreams(i).tDest <= toSlv(i, 8); @@ -570,9 +572,9 @@ begin U_DataFifoDebug : entity surf.SynchronizerFifo generic map ( - TPD_G => TPD_G, - DATA_WIDTH_G => 16, - ADDR_WIDTH_G => 4) + TPD_G => TPD_G, + DATA_WIDTH_G => 16, + ADDR_WIDTH_G => 4) port map ( rst => adcBitRstDiv4, wr_clk => adcBitClkDiv4, @@ -582,7 +584,7 @@ begin rd_en => debugDataValid(i), valid => debugDataValid(i), dout => debugData(i) - ); + ); end generate; From ca271a41cfe0258df9f7f7826a14281c85050149 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 6 Feb 2024 10:45:18 -0800 Subject: [PATCH 13/16] Apply bit reverse in readout2 --- .../ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd index 0a4a261023..4a86948b48 100644 --- a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd @@ -410,7 +410,8 @@ begin SIM_DEVICE_G => SIM_DEVICE_G, DEFAULT_DELAY_G => DEFAULT_DELAY_G, IDELAYCTRL_FREQ_G => 350.0, -- Check this - ADC_INVERT_CH_G => '0') + ADC_INVERT_CH_G => '0', + BIT_REV_G => '1') port map ( dClk => adcBitClk, dRst => adcBitRst, @@ -435,8 +436,9 @@ begin TPD_G => TPD_G, SIM_DEVICE_G => SIM_DEVICE_G, DEFAULT_DELAY_G => DEFAULT_DELAY_G, - IDELAYCTRL_FREQ_G => 350.0, -- Check this - ADC_INVERT_CH_G => ADC_INVERT_CH_G(ch)) -- Should maybe be '1' + IDELAYCTRL_FREQ_G => 350.0, -- Check this + ADC_INVERT_CH_G => ADC_INVERT_CH_G(ch), + BIT_REV_G => '1') -- Should maybe be '1' port map ( dClk => adcBitClk, dRst => adcBitRst, @@ -568,7 +570,7 @@ begin port map ( rst => adcBitRstDiv4, wr_clk => adcBitClkDiv4, - wr_en => adcFrameValid, --Always write data + wr_en => adcFrameValid, --Always write data din => fifoDataIn, rd_clk => axilClk, rd_en => debugDataValid, From f5fe4962cb5498c978d14a3a1005d9a79f92c507 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 7 Feb 2024 09:30:03 -0800 Subject: [PATCH 14/16] Bug fix, must copy param list not reference --- python/surf/xilinx/_Xadc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/python/surf/xilinx/_Xadc.py b/python/surf/xilinx/_Xadc.py index a53c99cefd..d256371c7c 100644 --- a/python/surf/xilinx/_Xadc.py +++ b/python/surf/xilinx/_Xadc.py @@ -30,7 +30,7 @@ def __init__(self, if isinstance(auxChannels, int): auxChannels = list(range(auxChannels)) - self.simpleViewList = simpleViewList + self.simpleViewList = simpleViewList[:] self.simpleViewList.append('enable') def addPair(name, offset, bitSize, units, bitOffset, description, function, pollInterval=0): From 4839d257b431f9580ce281f5fe82d4c634fcd27b Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 8 Feb 2024 16:32:54 -0800 Subject: [PATCH 15/16] Bug fix, must copy param list not reference --- python/surf/xilinx/_AxiSysMonUltraScale.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/python/surf/xilinx/_AxiSysMonUltraScale.py b/python/surf/xilinx/_AxiSysMonUltraScale.py index c2de0bf748..77b5ac87c3 100644 --- a/python/surf/xilinx/_AxiSysMonUltraScale.py +++ b/python/surf/xilinx/_AxiSysMonUltraScale.py @@ -20,7 +20,7 @@ def __init__( **kwargs): super().__init__(description=description, **kwargs) - self.simpleViewList = simpleViewList + self.simpleViewList = simpleViewList[:] def addPair(name, offset, bitSize, units, bitOffset, description, function, pollInterval=0): self.add(pr.RemoteVariable( From abd73550dc767090dc87bd1904011f0c6266fc1c Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Wed, 14 Feb 2024 17:13:33 -0800 Subject: [PATCH 16/16] bug fix for AxiSysMonUltraScale.py & Xadc.py when simpleViewList=None --- python/surf/xilinx/_AxiSysMonUltraScale.py | 19 ++++++++++--------- python/surf/xilinx/_Xadc.py | 9 +++++---- 2 files changed, 15 insertions(+), 13 deletions(-) diff --git a/python/surf/xilinx/_AxiSysMonUltraScale.py b/python/surf/xilinx/_AxiSysMonUltraScale.py index 77b5ac87c3..f2371904fc 100644 --- a/python/surf/xilinx/_AxiSysMonUltraScale.py +++ b/python/surf/xilinx/_AxiSysMonUltraScale.py @@ -20,7 +20,9 @@ def __init__( **kwargs): super().__init__(description=description, **kwargs) - self.simpleViewList = simpleViewList[:] + if simpleViewList is not None: + self.simpleViewList = simpleViewList[:] + self.simpleViewList.append('enable') def addPair(name, offset, bitSize, units, bitOffset, description, function, pollInterval=0): self.add(pr.RemoteVariable( @@ -528,8 +530,8 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll ) # Default to simple view - self.simpleView() - + if simpleViewList is not None: + self.simpleView() @staticmethod def convTempSYSMONE1(dev, var): @@ -568,9 +570,8 @@ def convAuxVoltage(var): return round(var.dependencies[0].value() * 244e-6,3) def simpleView(self): - if self.simpleViewList is not None: - # Hide all the variable - self.hideVariables(hidden=True) - # Then unhide the most interesting ones - vars = self.simpleViewList - self.hideVariables(hidden=False, variables=vars) + # Hide all the variable + self.hideVariables(hidden=True) + # Then unhide the most interesting ones + vars = self.simpleViewList + self.hideVariables(hidden=False, variables=vars) diff --git a/python/surf/xilinx/_Xadc.py b/python/surf/xilinx/_Xadc.py index d256371c7c..71bdd85dab 100644 --- a/python/surf/xilinx/_Xadc.py +++ b/python/surf/xilinx/_Xadc.py @@ -30,8 +30,9 @@ def __init__(self, if isinstance(auxChannels, int): auxChannels = list(range(auxChannels)) - self.simpleViewList = simpleViewList[:] - self.simpleViewList.append('enable') + if simpleViewList is not None: + self.simpleViewList = simpleViewList[:] + self.simpleViewList.append('enable') def addPair(name, offset, bitSize, units, bitOffset, description, function, pollInterval=0): self.add(pr.RemoteVariable( @@ -572,8 +573,8 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll ) # Default to simple view - self.simpleView() - + if simpleViewList is not None: + self.simpleView() @staticmethod def convTemp(dev, var):