From 01e4e3dab9e9fee3f94a8e34bf46894107c676db Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 7 Jul 2023 08:10:51 -0700 Subject: [PATCH 01/45] allowing RF block in gen1 type --- python/surf/xilinx/_RfTile.py | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/python/surf/xilinx/_RfTile.py b/python/surf/xilinx/_RfTile.py index e8ba4f8e4d..fed32f9872 100644 --- a/python/surf/xilinx/_RfTile.py +++ b/python/surf/xilinx/_RfTile.py @@ -196,14 +196,13 @@ def __init__( hidden = True, )) - if gen3: - prefix = 'adc' if isAdc else 'dac' - - for i in range(4): - self.add(xil.RfBlock( - name = f'{prefix}Block[{i}]', - isAdc = isAdc, - RestartSM = self.RestartSM, - offset = 0x2000 + 0x400*i, - expand = False, - )) + prefix = 'adc' if isAdc else 'dac' + + for i in range(4): + self.add(xil.RfBlock( + name = f'{prefix}Block[{i}]', + isAdc = isAdc, + RestartSM = self.RestartSM, + offset = 0x2000 + 0x400*i, + expand = False, + )) From 53cf2d8e659310de45c1d0262bf2b96da122a1ce Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Sun, 9 Jul 2023 10:23:48 -0700 Subject: [PATCH 02/45] migrating from .VCD to .GHW because GHW supports record type dumps --- tests/test_AxiStreamFifoV2IpIntegrator.py | 6 ++++-- tests/test_AxiVersionIpIntegrator.py | 6 ++++-- tests/test_DspComparator.py | 5 +++++ tests/test_LineCode10b12bTb.py | 6 ++++-- tests/test_LineCode12b14bTb.py | 6 ++++-- tests/test_LineCode8b10bTb.py | 6 ++++-- 6 files changed, 25 insertions(+), 10 deletions(-) diff --git a/tests/test_AxiStreamFifoV2IpIntegrator.py b/tests/test_AxiStreamFifoV2IpIntegrator.py index e35d7ca460..e9afe7c8d2 100644 --- a/tests/test_AxiStreamFifoV2IpIntegrator.py +++ b/tests/test_AxiStreamFifoV2IpIntegrator.py @@ -195,6 +195,8 @@ def test_AxiStreamFifoV2IpIntegrator(parameters): # When two operators are overloaded, give preference to the explicit declaration (-fexplicit) vhdl_compile_args = ['-fsynopsys','-frelaxed-rules', '-fexplicit'], - # Dump waveform to file ($ gtkwave sim_build/AxiStreamFifoV2IpIntegrator/AxiStreamFifoV2IpIntegrator.vcd) - sim_args =[f'--vcd={tests_module}.vcd'], + ######################################################################## + # Dump waveform to file ($ gtkwave sim_build/path/To/{tests_module}.ghw) + ######################################################################## + # sim_args =[f'--wave={tests_module}.ghw'], ) diff --git a/tests/test_AxiVersionIpIntegrator.py b/tests/test_AxiVersionIpIntegrator.py index 520ea76dc6..32fffb491a 100644 --- a/tests/test_AxiVersionIpIntegrator.py +++ b/tests/test_AxiVersionIpIntegrator.py @@ -130,6 +130,8 @@ def test_AxiVersionIpIntegrator(parameters): # -frelaxed-rules option to allow IP integrator attributes vhdl_compile_args = ['-fsynopsys','-frelaxed-rules'], - # Dump waveform to file ($ gtkwave sim_build/AxiVersionIpIntegrator/AxiVersionIpIntegrator.vcd) - sim_args =[f'--vcd={tests_module}.vcd'], + ######################################################################## + # Dump waveform to file ($ gtkwave sim_build/path/To/{tests_module}.ghw) + ######################################################################## + # sim_args =[f'--wave={tests_module}.ghw'], ) diff --git a/tests/test_DspComparator.py b/tests/test_DspComparator.py index 85b4673633..b06634d10a 100644 --- a/tests/test_DspComparator.py +++ b/tests/test_DspComparator.py @@ -161,4 +161,9 @@ def test_DspComparator(parameters): # Select a simulator simulator="ghdl", + + ######################################################################## + # Dump waveform to file ($ gtkwave sim_build/path/To/{tests_module}.ghw) + ######################################################################## + # sim_args =[f'--wave={tests_module}.ghw'], ) diff --git a/tests/test_LineCode10b12bTb.py b/tests/test_LineCode10b12bTb.py index a87dac1f2f..ed76db45ca 100644 --- a/tests/test_LineCode10b12bTb.py +++ b/tests/test_LineCode10b12bTb.py @@ -169,6 +169,8 @@ def test_LineCode10b12bTb(parameters): # When two operators are overloaded, give preference to the explicit declaration (-fexplicit) vhdl_compile_args = ['-fsynopsys', '-fexplicit'], - # Dump waveform to file ($ gtkwave sim_build/LineCode12b14bTb./LineCode12b14bTb.vcd) - sim_args =[f'--vcd={tests_module}.vcd'], + ######################################################################## + # Dump waveform to file ($ gtkwave sim_build/path/To/{tests_module}.ghw) + ######################################################################## + # sim_args =[f'--wave={tests_module}.ghw'], ) diff --git a/tests/test_LineCode12b14bTb.py b/tests/test_LineCode12b14bTb.py index 05bd7d03c0..fdd4c0f817 100644 --- a/tests/test_LineCode12b14bTb.py +++ b/tests/test_LineCode12b14bTb.py @@ -233,6 +233,8 @@ def test_LineCode12b14bTb(parameters): # When two operators are overloaded, give preference to the explicit declaration (-fexplicit) vhdl_compile_args = ['-fsynopsys', '-fexplicit'], - # Dump waveform to file ($ gtkwave sim_build/LineCode12b14bTb./LineCode12b14bTb.vcd) - sim_args =[f'--vcd={tests_module}.vcd'], + ######################################################################## + # Dump waveform to file ($ gtkwave sim_build/path/To/{tests_module}.ghw) + ######################################################################## + # sim_args =[f'--wave={tests_module}.ghw'], ) diff --git a/tests/test_LineCode8b10bTb.py b/tests/test_LineCode8b10bTb.py index 4da7ca93ba..8c6f065362 100644 --- a/tests/test_LineCode8b10bTb.py +++ b/tests/test_LineCode8b10bTb.py @@ -162,6 +162,8 @@ def test_LineCode8b10bTb(parameters): # Select a simulator simulator="ghdl", - # Dump waveform to file ($ gtkwave sim_build/LineCode8b10bTb.NUM_BYTES_G\=1/LineCode8b10bTb.vcd) - sim_args =[f'--vcd={tests_module}.vcd'], + ######################################################################## + # Dump waveform to file ($ gtkwave sim_build/path/To/{tests_module}.ghw) + ######################################################################## + # sim_args =[f'--wave={tests_module}.ghw'], ) From 010b9c44982fa0ab9e6ee2c4634d064ca3b579db Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Sun, 9 Jul 2023 13:43:22 -0700 Subject: [PATCH 03/45] bug fixes for AxiStreamGearbox.vhd --- axi/axi-stream/rtl/AxiStreamGearbox.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/axi/axi-stream/rtl/AxiStreamGearbox.vhd b/axi/axi-stream/rtl/AxiStreamGearbox.vhd index 05e7411855..30a785eae6 100644 --- a/axi/axi-stream/rtl/AxiStreamGearbox.vhd +++ b/axi/axi-stream/rtl/AxiStreamGearbox.vhd @@ -72,7 +72,7 @@ architecture rtl of AxiStreamGearbox is constant MAX_C : positive := maximum(MST_BYTES_C, SLV_BYTES_C); constant MIN_C : positive := minimum(MST_BYTES_C, SLV_BYTES_C); - constant SHIFT_WIDTH_C : positive := wordCount(MAX_C, MIN_C) * MIN_C + MIN_C; + constant SHIFT_WIDTH_C : positive := wordCount(MAX_C, MIN_C) * MIN_C + MIN_C + 1; type RegType is record writeIndex : natural range 0 to SHIFT_WIDTH_C-1; @@ -265,7 +265,7 @@ begin end if; -- Increment writeIndex - v.writeIndex := v.writeIndex + SLV_BYTES_C; + v.writeIndex := v.writeIndex + getTKeep(resize(sAxisMaster.tKeep(1*SLV_BYTES_C-1 downto 0), AXI_STREAM_MAX_TKEEP_WIDTH_C), SLAVE_AXI_CONFIG_G); -- Assert tValid if (v.writeIndex >= MST_BYTES_C) or (sAxisMaster.tLast = '1') then From 4a90a1e7598f1fd3a5ea90f42cc30050272cd2e9 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Sun, 9 Jul 2023 14:09:42 -0700 Subject: [PATCH 04/45] bug fixes for AxiStreamGearbox.vhd for when (SLV_BYTES_C>2*MST_BYTES_C) and terminating a frame --- axi/axi-stream/rtl/AxiStreamGearbox.vhd | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/axi/axi-stream/rtl/AxiStreamGearbox.vhd b/axi/axi-stream/rtl/AxiStreamGearbox.vhd index 30a785eae6..0901b7f163 100644 --- a/axi/axi-stream/rtl/AxiStreamGearbox.vhd +++ b/axi/axi-stream/rtl/AxiStreamGearbox.vhd @@ -72,7 +72,7 @@ architecture rtl of AxiStreamGearbox is constant MAX_C : positive := maximum(MST_BYTES_C, SLV_BYTES_C); constant MIN_C : positive := minimum(MST_BYTES_C, SLV_BYTES_C); - constant SHIFT_WIDTH_C : positive := wordCount(MAX_C, MIN_C) * MIN_C + MIN_C + 1; + constant SHIFT_WIDTH_C : positive := wordCount(MAX_C, MIN_C) * MIN_C + MIN_C; type RegType is record writeIndex : natural range 0 to SHIFT_WIDTH_C-1; @@ -212,8 +212,10 @@ begin -- Set the flags v.tValid := '1'; - v.tLast := r.tLastDly; - v.tLastDly := '0'; + if (v.writeIndex <= MST_BYTES_C) then + v.tLast := r.tLastDly; + v.tLastDly := '0'; + end if; end if; From 22f55b66bcceee8722fb07242bed8c100dd4f2ea Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Sun, 9 Jul 2023 14:12:26 -0700 Subject: [PATCH 05/45] updating paramSweep to include non-word multiple to execise AxiStreamGearbox --- tests/test_AxiStreamFifoV2IpIntegrator.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/tests/test_AxiStreamFifoV2IpIntegrator.py b/tests/test_AxiStreamFifoV2IpIntegrator.py index e9afe7c8d2..641d419970 100644 --- a/tests/test_AxiStreamFifoV2IpIntegrator.py +++ b/tests/test_AxiStreamFifoV2IpIntegrator.py @@ -87,6 +87,10 @@ async def m_cycle_reset(self): async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None): + # Debug messages in case it fails + dut._log.info( f'Found M_TDATA_NUM_BYTES={dut.M_TDATA_NUM_BYTES.value.integer}' ) + dut._log.info( f'Found S_TDATA_NUM_BYTES={dut.S_TDATA_NUM_BYTES.value.integer}' ) + tb = TB(dut) id_count = 2**len(tb.source.bus.tid) @@ -144,8 +148,8 @@ def incrementing_payload(length): ############################################################################## paramSweep = [] -for sTdataByte in ['2','6']: - for mTdataByte in ['2','6']: +for sTdataByte in ['2','5','6']: + for mTdataByte in ['2','5','6']: tmpDict = { "M_TDATA_NUM_BYTES": mTdataByte, "S_TDATA_NUM_BYTES": sTdataByte, From 8a6243448dd58888f13ae1325835dbbde8eff30d Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 20 Jul 2023 13:15:42 -0700 Subject: [PATCH 06/45] adding test_AxiStreamDemuxMuxTb.py --- axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd | 175 +++++++++++++++++++++ tests/test_AxiStreamDemuxMuxTb.py | 180 ++++++++++++++++++++++ 2 files changed, 355 insertions(+) create mode 100644 axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd create mode 100644 tests/test_AxiStreamDemuxMuxTb.py diff --git a/axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd b/axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd new file mode 100644 index 0000000000..4300c9d7a3 --- /dev/null +++ b/axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd @@ -0,0 +1,175 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: IP Integrator Wrapper for surf.AxiStreamFifoV2 +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; + +entity AxiStreamDemuxMuxTb is + generic ( + -- AXI Stream Configuration + TUSER_WIDTH_G : positive range 1 to 8 := 1; + TID_WIDTH_G : positive range 1 to 8 := 1; + TDEST_WIDTH_G : positive range 1 to 8 := 1; + TDATA_NUM_BYTES_G : positive range 1 to 128 := 1; + MUX_STREAMS_G : positive := 2; + PIPE_STAGES_G : natural := 0; + ILEAVE_EN_G : boolean := false; + ILEAVE_ON_NOTVALID_G : boolean := false; + ILEAVE_REARB_G : natural := 0; + REARB_DELAY_G : boolean := true; + FORCED_REARB_HOLD_G : boolean := false); + port ( + -- Clock and Reset + AXIS_ACLK : in std_logic := '0'; + AXIS_ARESETN : in std_logic := '0'; + -- IP Integrator Slave AXI Stream Interface + S_AXIS_TVALID : in std_logic := '0'; + S_AXIS_TDATA : in std_logic_vector((8*TDATA_NUM_BYTES_G)-1 downto 0) := (others => '0'); + S_AXIS_TSTRB : in std_logic_vector(TDATA_NUM_BYTES_G-1 downto 0) := (others => '0'); + S_AXIS_TKEEP : in std_logic_vector(TDATA_NUM_BYTES_G-1 downto 0) := (others => '0'); + S_AXIS_TLAST : in std_logic := '0'; + S_AXIS_TDEST : in std_logic_vector(TDEST_WIDTH_G-1 downto 0) := (others => '0'); + S_AXIS_TID : in std_logic_vector(TID_WIDTH_G-1 downto 0) := (others => '0'); + S_AXIS_TUSER : in std_logic_vector(TUSER_WIDTH_G-1 downto 0) := (others => '0'); + S_AXIS_TREADY : out std_logic; + -- IP Integrator Master AXI Stream Interface + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector((8*TDATA_NUM_BYTES_G)-1 downto 0); + M_AXIS_TSTRB : out std_logic_vector(TDATA_NUM_BYTES_G-1 downto 0); + M_AXIS_TKEEP : out std_logic_vector(TDATA_NUM_BYTES_G-1 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TDEST : out std_logic_vector(TDEST_WIDTH_G-1 downto 0); + M_AXIS_TID : out std_logic_vector(TID_WIDTH_G-1 downto 0); + M_AXIS_TUSER : out std_logic_vector(TUSER_WIDTH_G-1 downto 0); + M_AXIS_TREADY : in std_logic); +end AxiStreamDemuxMuxTb; + +architecture mapping of AxiStreamDemuxMuxTb is + + signal axisClk : sl := '0'; + signal axisRst : sl := '0'; + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + + signal axisMasters : AxiStreamMasterArray(MUX_STREAMS_G-1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal axisSlaves : AxiStreamSlaveArray(MUX_STREAMS_G-1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); + + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + +begin + + U_ShimLayerSlave : entity surf.SlaveAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "S_AXIS", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 1, + HAS_TREADY => 1, + TUSER_WIDTH => TUSER_WIDTH_G, + TID_WIDTH => TID_WIDTH_G, + TDEST_WIDTH => TDEST_WIDTH_G, + TDATA_NUM_BYTES => TDATA_NUM_BYTES_G) + port map ( + -- IP Integrator AXI Stream Interface + S_AXIS_ACLK => AXIS_ACLK, + S_AXIS_ARESETN => AXIS_ARESETN, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TSTRB => S_AXIS_TSTRB, + S_AXIS_TKEEP => S_AXIS_TKEEP, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TDEST => S_AXIS_TDEST, + S_AXIS_TID => S_AXIS_TID, + S_AXIS_TUSER => S_AXIS_TUSER, + S_AXIS_TREADY => S_AXIS_TREADY, + -- SURF AXI Stream Interface + axisClk => axisClk, + axisRst => axisRst, + axisMaster => sAxisMaster, + axisSlave => sAxisSlave); + + U_DeMux : entity surf.AxiStreamDeMux + generic map ( + NUM_MASTERS_G => MUX_STREAMS_G, + PIPE_STAGES_G => PIPE_STAGES_G) + port map ( + -- Clock and reset + axisClk => axisClk, + axisRst => axisRst, + -- Slave + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + -- Masters + mAxisMasters => axisMasters, + mAxisSlaves => axisSlaves); + + U_Mux : entity surf.AxiStreamMux + generic map ( + NUM_SLAVES_G => MUX_STREAMS_G, + PIPE_STAGES_G => PIPE_STAGES_G, + ILEAVE_EN_G => ILEAVE_EN_G, + ILEAVE_ON_NOTVALID_G => ILEAVE_ON_NOTVALID_G, + ILEAVE_REARB_G => ILEAVE_REARB_G, + REARB_DELAY_G => REARB_DELAY_G, + FORCED_REARB_HOLD_G => FORCED_REARB_HOLD_G) + port map ( + -- Clock and reset + axisClk => axisClk, + axisRst => axisRst, + -- Slaves + sAxisMasters => axisMasters, + sAxisSlaves => axisSlaves, + -- Master + mAxisMaster => mAxisMaster, + mAxisSlave => mAxisSlave); + + U_ShimLayerMaster : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "M_AXIS", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 1, + HAS_TREADY => 1, + TUSER_WIDTH => TUSER_WIDTH_G, + TID_WIDTH => TID_WIDTH_G, + TDEST_WIDTH => TDEST_WIDTH_G, + TDATA_NUM_BYTES => TDATA_NUM_BYTES_G) + port map ( + -- IP Integrator AXI Stream Interface + M_AXIS_ACLK => AXIS_ACLK, + M_AXIS_ARESETN => AXIS_ARESETN, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TSTRB => M_AXIS_TSTRB, + M_AXIS_TKEEP => M_AXIS_TKEEP, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TDEST => M_AXIS_TDEST, + M_AXIS_TID => M_AXIS_TID, + M_AXIS_TUSER => M_AXIS_TUSER, + M_AXIS_TREADY => M_AXIS_TREADY, + -- SURF AXI Stream Interface + axisClk => open, + axisRst => open, + axisMaster => mAxisMaster, + axisSlave => mAxisSlave); + +end mapping; diff --git a/tests/test_AxiStreamDemuxMuxTb.py b/tests/test_AxiStreamDemuxMuxTb.py new file mode 100644 index 0000000000..4a31856021 --- /dev/null +++ b/tests/test_AxiStreamDemuxMuxTb.py @@ -0,0 +1,180 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# dut_tb +import itertools +import logging +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge +from cocotb.regression import TestFactory + +from cocotbext.axi import AxiStreamFrame, AxiStreamBus, AxiStreamSource, AxiStreamSink + +# test_AxiStreamDemuxMuxTb +from cocotb_test.simulator import run +import pytest +import glob +import os + +class TB: + def __init__(self, dut): + + # Pointer to DUT object + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + # Start AXIS_ACLK clock (200 MHz) in a separate thread + cocotb.start_soon(Clock(dut.AXIS_ACLK, 5.0, units='ns').start()) + + # Setup the AXI stream source + self.source = AxiStreamSource( + bus = AxiStreamBus.from_prefix(dut, "S_AXIS"), + clock = dut.AXIS_ACLK, + reset = dut.AXIS_ARESETN, + reset_active_level = False, + ) + + # Setup the AXI stream sink + self.sink = AxiStreamSink( + bus = AxiStreamBus.from_prefix(dut, "M_AXIS"), + clock = dut.AXIS_ACLK, + reset = dut.AXIS_ARESETN, + reset_active_level = False, + ) + + def set_idle_generator(self, generator=None): + if generator: + self.source.set_pause_generator(generator()) + + def set_backpressure_generator(self, generator=None): + if generator: + self.sink.set_pause_generator(generator()) + + async def cycle_reset(self): + self.dut.AXIS_ARESETN.setimmediatevalue(0) + await RisingEdge(self.dut.AXIS_ACLK) + await RisingEdge(self.dut.AXIS_ACLK) + self.dut.AXIS_ARESETN.value = 0 + await RisingEdge(self.dut.AXIS_ACLK) + await RisingEdge(self.dut.AXIS_ACLK) + self.dut.AXIS_ARESETN.value = 1 + await RisingEdge(self.dut.AXIS_ACLK) + await RisingEdge(self.dut.AXIS_ACLK) + +async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + id_count = 2**len(tb.source.bus.tid) + + cur_id = 1 + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + test_frames = [] + + for test_data in [payload_data(x) for x in payload_lengths()]: + test_frame = AxiStreamFrame(test_data) + test_frame.tid = cur_id + test_frame.tdest = cur_id + await tb.source.send(test_frame) + + test_frames.append(test_frame) + + cur_id = (cur_id + 1) % id_count + + for test_frame in test_frames: + rx_frame = await tb.sink.recv() + + assert rx_frame.tdata == test_frame.tdata + assert rx_frame.tid == test_frame.tid + assert rx_frame.tdest == test_frame.tdest + assert not rx_frame.tuser + + assert tb.sink.empty() + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + +def size_list(): + return list(range(1, 32+1)) + +def incrementing_payload(length): + return bytearray(itertools.islice(itertools.cycle(range(256)), length)) + +if cocotb.SIM_NAME: + factory = TestFactory(run_test) + factory.add_option("payload_lengths", [size_list]) + factory.add_option("payload_data", [incrementing_payload]) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.generate_tests() + +tests_dir = os.path.dirname(__file__) +tests_module = 'AxiStreamDemuxMuxTb' + +############################################################################## + +@pytest.mark.parametrize( + "parameters", [ + {'MUX_STREAMS_G': '2', 'PIPE_STAGES_G': '0'}, + {'MUX_STREAMS_G': '3', 'PIPE_STAGES_G': '1'}, + ]) +def test_AxiStreamDemuxMuxTb(parameters): + + # https://github.com/themperek/cocotb-test#arguments-for-simulatorrun + # https://github.com/themperek/cocotb-test/blob/master/cocotb_test/simulator.py + run( + # top level HDL + toplevel = f'surf.{tests_module}'.lower(), + + # name of the file that contains @cocotb.test() -- this file + # https://docs.cocotb.org/en/stable/building.html?#envvar-MODULE + module = f'test_{tests_module}', + + # https://docs.cocotb.org/en/stable/building.html?#var-TOPLEVEL_LANG + toplevel_lang = 'vhdl', + + # VHDL source files to include. + # Can be specified as a list or as a dict of lists with the library name as key, + # if the simulator supports named libraries. + vhdl_sources = { + 'surf' : glob.glob(f'{tests_dir}/../build/SRC_VHDL/surf/*'), + 'ruckus' : glob.glob(f'{tests_dir}/../build/SRC_VHDL/ruckus/*'), + }, + + # A dictionary of top-level parameters/generics. + parameters = parameters, + + # The directory used to compile the tests. (default: sim_build) + sim_build = f'{tests_dir}/sim_build/{tests_module}.' + ",".join((f"{key}={value}" for key, value in parameters.items())), + + # A dictionary of extra environment variables set in simulator process. + extra_env=parameters, + + # Select a simulator + simulator="ghdl", + + # use of synopsys package "std_logic_arith" needs the -fsynopsys option + # -frelaxed-rules option to allow IP integrator attributes + # When two operators are overloaded, give preference to the explicit declaration (-fexplicit) + vhdl_compile_args = ['-fsynopsys','-frelaxed-rules', '-fexplicit'], + + ######################################################################## + # Dump waveform to file ($ gtkwave sim_build/path/To/{tests_module}.ghw) + ######################################################################## + # sim_args =[f'--wave={tests_module}.ghw'], + ) From 801ad8d3f77ea90c6a7e242ad1d0fecebfe642b1 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 20 Jul 2023 15:43:23 -0700 Subject: [PATCH 07/45] code clean up --- axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd | 2 +- tests/test_LineCode10b12bTb.py | 2 +- tests/test_LineCode12b14bTb.py | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd b/axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd index 4300c9d7a3..330106d80e 100644 --- a/axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd +++ b/axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- --- Description: IP Integrator Wrapper for surf.AxiStreamFifoV2 +-- Description: surf.AxiStreamDemux/surf.AxiStreamMux cocoTB testbed ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the diff --git a/tests/test_LineCode10b12bTb.py b/tests/test_LineCode10b12bTb.py index ed76db45ca..099cb906e3 100644 --- a/tests/test_LineCode10b12bTb.py +++ b/tests/test_LineCode10b12bTb.py @@ -157,7 +157,7 @@ def test_LineCode10b12bTb(parameters): parameters = parameters, # The directory used to compile the tests. (default: sim_build) - sim_build = f'{tests_dir}/sim_build/{tests_module}.', + sim_build = f'{tests_dir}/sim_build/{tests_module}', # A dictionary of extra environment variables set in simulator process. extra_env=parameters, diff --git a/tests/test_LineCode12b14bTb.py b/tests/test_LineCode12b14bTb.py index fdd4c0f817..f429e68937 100644 --- a/tests/test_LineCode12b14bTb.py +++ b/tests/test_LineCode12b14bTb.py @@ -221,7 +221,7 @@ def test_LineCode12b14bTb(parameters): parameters = parameters, # The directory used to compile the tests. (default: sim_build) - sim_build = f'{tests_dir}/sim_build/{tests_module}.', + sim_build = f'{tests_dir}/sim_build/{tests_module}', # A dictionary of extra environment variables set in simulator process. extra_env=parameters, From e82ca430b90175c619ae5a03b6be679a1ead59fc Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 21 Jul 2023 13:07:34 -0700 Subject: [PATCH 08/45] Add initialization values for tx registers --- protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd | 85 +------------------ protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd | 64 +++++++------- protocols/pgp/pgp2b/core/rtl/Pgp2bTxPhy.vhd | 22 ++--- protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd | 22 ++--- 4 files changed, 56 insertions(+), 137 deletions(-) diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd index baf6c5cf88..3602ecd79c 100644 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd @@ -5,87 +5,6 @@ ------------------------------------------------------------------------------- -- Description: -- AXI-Lite block to manage the PGP interface. --- --- Address map (offset from base): --- 0x00 = Read/Write --- Bits 0 = Count Reset --- 0x04 = Read/Write --- Bits 0 = Reset Rx --- 0x08 = Read/Write --- Bits 0 = Flush --- 0x0C = Read/Write --- Bits 1:0 = Loop Back --- 0x10 = Read/Write --- Bits 7:0 = Sideband data to transmit --- Bits 8 = Sideband data enable --- 0x14 = Read/Write --- Bits 0 = Auto Status Send Enable (PPI) --- 0x18 = Read/Write --- Bits 0 = Disable Flow Control --- 0x20 = Read Only --- Bits 0 = Rx Phy Ready --- Bits 1 = Tx Phy Ready --- Bits 2 = Local Link Ready --- Bits 3 = Remote Link Ready --- Bits 4 = Transmit Ready --- Bits 9:8 = Receive Link Polarity --- Bits 15:12 = Remote Pause Status --- Bits 19:16 = Local Pause Status --- Bits 23:20 = Remote Overflow Status --- Bits 27:24 = Local Overflow Status --- 0x24 = Read Only --- Bits 7:0 = Remote Link Data --- 0x28 = Read Only --- Bits ?:0 = Cell Error Count --- 0x2C = Read Only --- Bits ?:0 = Link Down Count --- 0x30 = Read Only --- Bits ?:0 = Link Error Count --- 0x34 = Read Only --- Bits ?:0 = Remote Overflow VC 0 Count --- 0x38 = Read Only --- Bits ?:0 = Remote Overflow VC 1 Count --- 0x3C = Read Only --- Bits ?:0 = Remote Overflow VC 2 Count --- 0x40 = Read Only --- Bits ?:0 = Remote Overflow VC 3 Count --- 0x44 = Read Only --- Bits ?:0 = Receive Frame Error Count --- 0x48 = Read Only --- Bits ?:0 = Receive Frame Count --- 0x4C = Read Only --- Bits ?:0 = Local Overflow VC 0 Count --- 0x50 = Read Only --- Bits ?:0 = Local Overflow VC 1 Count --- 0x54 = Read Only --- Bits ?:0 = Local Overflow VC 2 Count --- 0x58 = Read Only --- Bits ?:0 = Local Overflow VC 3 Count --- 0x5C = Read Only --- Bits ?:0 = Transmit Frame Error Count --- 0x60 = Read Only --- Bits ?:0 = Transmit Frame Count --- 0x64 = Read Only --- Bits 31:0 = Receive Clock Frequency --- 0x68 = Read Only --- Bits 31:0 = Transmit Clock Frequency --- 0x70 = Read Only --- Bits 7:0 = Last OpCode Transmitted --- 0x74 = Read Only --- Bits 7:0 = Last OpCode Received --- 0x78 = Read Only --- Bits ?:0 = OpCode Transmit count --- 0x7C = Read Only --- Bits ?:0 = OpCode Received count --- --- Status vector: --- Bits 31:24 = Rx Link Down Count --- Bits 23:16 = Rx Frame Error Count --- Bits 15:8 = Rx Cell Error Count --- Bits 7:6 = Zeros --- Bits 5 = Remote Link Ready --- Bits 4 = Local Link Ready --- Bits 3:0 = Remote Overflow Status ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the @@ -400,7 +319,7 @@ begin generic map ( TPD_G => TPD_G, REF_CLK_FREQ_G => AXI_CLK_FREQ_G, - REFRESH_RATE_G => 100.0, + REFRESH_RATE_G => 1000.0, CLK_LOWER_LIMIT_G => 155.0E+6, CLK_UPPER_LIMIT_G => 158.0E+6, CNT_WIDTH_G => 32) @@ -515,7 +434,7 @@ begin generic map ( TPD_G => TPD_G, REF_CLK_FREQ_G => AXI_CLK_FREQ_G, - REFRESH_RATE_G => 100.0, + REFRESH_RATE_G => 1000.0, CLK_LOWER_LIMIT_G => 155.0E+6, CLK_UPPER_LIMIT_G => 158.0E+6, CNT_WIDTH_G => 32) diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd index 1ff581ef07..bd5316cd87 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd @@ -41,16 +41,16 @@ entity Pgp2bTxCell is pgpTxLinkReady : in sl; -- Local side has link -- Phy Transmit Interface - cellTxSOC : out sl; -- Cell data start of cell - cellTxSOF : out sl; -- Cell data start of frame - cellTxEOC : out sl; -- Cell data end of cell - cellTxEOF : out sl; -- Cell data end of frame - cellTxEOFE : out sl; -- Cell data end of frame error - cellTxData : out slv(TX_LANE_CNT_G*16-1 downto 0); -- Cell data data + cellTxSOC : out sl := '0'; -- Cell data start of cell + cellTxSOF : out sl := '0'; -- Cell data start of frame + cellTxEOC : out sl := '0'; -- Cell data end of cell + cellTxEOF : out sl := '0'; -- Cell data end of frame + cellTxEOFE : out sl := '0'; -- Cell data end of frame error + cellTxData : out slv(TX_LANE_CNT_G*16-1 downto 0) := (others => '0'); -- Cell data data -- Transmit Scheduler Interface - schTxSOF : out sl; -- Cell contained SOF - schTxEOF : out sl; -- Cell contained EOF + schTxSOF : out sl := '0'; -- Cell contained SOF + schTxEOF : out sl := '0'; -- Cell contained EOF schTxIdle : in sl; -- Force IDLE transmit schTxReq : in sl; -- Cell transmit request schTxAck : out sl; -- Cell transmit acknowledge @@ -121,12 +121,12 @@ architecture Pgp2bTxCell of Pgp2bTxCell is signal muxFrameTxEOFE : sl; signal muxFrameTxData : slv(TX_LANE_CNT_G*16-1 downto 0); signal muxRemAlmostFull : sl; - signal cellCnt : slv(PAYLOAD_CNT_TOP_G downto 0); + signal cellCnt : slv(PAYLOAD_CNT_TOP_G downto 0) := (others => '0'); signal cellCntRst : sl; signal nxtFrameTxReady : sl; signal nxtType : slv(2 downto 0); signal nxtTypeLast : slv(2 downto 0); - signal curTypeLast : slv(2 downto 0); + signal curTypeLast : slv(2 downto 0) := (others => '0'); signal nxtTxSOF : sl; signal nxtTxEOF : sl; signal nxtTxAck : sl; @@ -136,27 +136,27 @@ architecture Pgp2bTxCell of Pgp2bTxCell is signal crcWordA : slv(TX_LANE_CNT_G*16-1 downto 0); signal crcWordB : slv(TX_LANE_CNT_G*16-1 downto 0); signal serialCntEn : sl; - signal vc0Serial : slv(5 downto 0); - signal vc1Serial : slv(5 downto 0); - signal vc2Serial : slv(5 downto 0); - signal vc3Serial : slv(5 downto 0); + signal vc0Serial : slv(5 downto 0) := (others => '0'); + signal vc1Serial : slv(5 downto 0) := (others => '0'); + signal vc2Serial : slv(5 downto 0) := (others => '0'); + signal vc3Serial : slv(5 downto 0) := (others => '0'); signal muxSerial : slv(5 downto 0); - signal dly0Data : slv(TX_LANE_CNT_G*16-1 downto 0); - signal dly0Type : slv(2 downto 0); - signal dly1Data : slv(TX_LANE_CNT_G*16-1 downto 0); - signal dly1Type : slv(2 downto 0); - signal dly2Data : slv(TX_LANE_CNT_G*16-1 downto 0); - signal dly2Type : slv(2 downto 0); - signal dly3Data : slv(TX_LANE_CNT_G*16-1 downto 0); - signal dly3Type : slv(2 downto 0); - signal dly4Data : slv(TX_LANE_CNT_G*16-1 downto 0); - signal dly4Type : slv(2 downto 0); - signal int0FrameTxReady : sl; - signal int1FrameTxReady : sl; - signal int2FrameTxReady : sl; - signal int3FrameTxReady : sl; - signal intTimeout : sl; - signal intOverflow : slv(3 downto 0); + signal dly0Data : slv(TX_LANE_CNT_G*16-1 downto 0) := (others => '0'); + signal dly0Type : slv(2 downto 0) := (others => '0'); + signal dly1Data : slv(TX_LANE_CNT_G*16-1 downto 0) := (others => '0'); + signal dly1Type : slv(2 downto 0) := (others => '0'); + signal dly2Data : slv(TX_LANE_CNT_G*16-1 downto 0) := (others => '0'); + signal dly2Type : slv(2 downto 0) := (others => '0'); + signal dly3Data : slv(TX_LANE_CNT_G*16-1 downto 0) := (others => '0'); + signal dly3Type : slv(2 downto 0) := (others => '0'); + signal dly4Data : slv(TX_LANE_CNT_G*16-1 downto 0) := (others => '0'); + signal dly4Type : slv(2 downto 0) := (others => '0'); + signal int0FrameTxReady : sl := '0'; + signal int1FrameTxReady : sl := '0'; + signal int2FrameTxReady : sl := '0'; + signal int3FrameTxReady : sl := '0'; + signal intTimeout : sl := '0'; + signal intOverflow : slv(3 downto 0) := (others => '0'); -- Transmit Data Marker constant TX_DATA_C : slv(2 downto 0) := "000"; @@ -169,8 +169,6 @@ architecture Pgp2bTxCell of Pgp2bTxCell is constant TX_CRCB_C : slv(2 downto 0) := "111"; -- Transmit states - signal curState : slv(2 downto 0); - signal nxtState : slv(2 downto 0); constant ST_IDLE_C : slv(2 downto 0) := "001"; constant ST_EMPTY_C : slv(2 downto 0) := "010"; constant ST_SOC_C : slv(2 downto 0) := "011"; @@ -178,6 +176,8 @@ architecture Pgp2bTxCell of Pgp2bTxCell is constant ST_CRCA_C : slv(2 downto 0) := "101"; constant ST_CRCB_C : slv(2 downto 0) := "110"; constant ST_EOC_C : slv(2 downto 0) := "111"; + signal curState : slv(2 downto 0) := ST_IDLE_C; + signal nxtState : slv(2 downto 0); begin diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxPhy.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxPhy.vhd index 55c99c2930..7b2269bc55 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxPhy.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxPhy.vhd @@ -68,19 +68,19 @@ end Pgp2bTxPhy; architecture Pgp2bTxPhy of Pgp2bTxPhy is -- Local Signals - signal algnCnt : slv(6 downto 0); + signal algnCnt : slv(6 downto 0) := (others => '0'); signal algnCntRst : sl; - signal intTxLinkReady : sl; + signal intTxLinkReady : sl := '0'; signal nxtTxLinkReady : sl; signal nxtTxData : slv(TX_LANE_CNT_G*16-1 downto 0); signal nxtTxDataK : slv(TX_LANE_CNT_G*2-1 downto 0); - signal dlyTxData : slv(TX_LANE_CNT_G*16-1 downto 0); - signal dlyTxDataK : slv(TX_LANE_CNT_G*2-1 downto 0); - signal dlySelect : sl; - signal intTxData : slv(TX_LANE_CNT_G*16-1 downto 0); - signal intTxDataK : slv(TX_LANE_CNT_G*2-1 downto 0); - signal intTxOpCode : slv(7 downto 0); - signal intTxOpCodeEn : sl; + signal dlyTxData : slv(TX_LANE_CNT_G*16-1 downto 0) := (others => '0'); + signal dlyTxDataK : slv(TX_LANE_CNT_G*2-1 downto 0) := (others => '0'); + signal dlySelect : sl := '0'; + signal intTxData : slv(TX_LANE_CNT_G*16-1 downto 0) := (others => '0'); + signal intTxDataK : slv(TX_LANE_CNT_G*2-1 downto 0) := (others => '0'); + signal intTxOpCode : slv(7 downto 0) := (others => '0'); + signal intTxOpCodeEn : sl := '0'; signal skpAData : slv(TX_LANE_CNT_G*16-1 downto 0); signal skpADataK : slv(TX_LANE_CNT_G*2-1 downto 0); signal skpBData : slv(TX_LANE_CNT_G*16-1 downto 0); @@ -95,7 +95,7 @@ architecture Pgp2bTxPhy of Pgp2bTxPhy is signal ltsBDataK : slv(TX_LANE_CNT_G*2-1 downto 0); signal cellData : slv(TX_LANE_CNT_G*16-1 downto 0); signal cellDataK : slv(TX_LANE_CNT_G*2-1 downto 0); - signal dlyTxEOC : sl; + signal dlyTxEOC : sl := '0'; -- Physical Link State constant ST_LOCK_C : slv(3 downto 0) := "0000"; @@ -107,7 +107,7 @@ architecture Pgp2bTxPhy of Pgp2bTxPhy is constant ST_ALN_B_C : slv(3 downto 0) := "0110"; constant ST_CELL_C : slv(3 downto 0) := "0111"; constant ST_EMPTY_C : slv(3 downto 0) := "1000"; - signal curState : slv(3 downto 0); + signal curState : slv(3 downto 0) := ST_LOCK_C; signal nxtState : slv(3 downto 0); begin diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd index 149f406368..2ec0b9534e 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd @@ -73,22 +73,22 @@ architecture Pgp2bTxSched of Pgp2bTxSched is -- Local Signals signal currValid : sl; - signal currVc : slv(1 downto 0); + signal currVc : slv(1 downto 0) := (others => '0'); signal nextVc : slv(1 downto 0); signal arbVc : slv(1 downto 0); signal arbValid : sl; - signal vcInFrame : slv(3 downto 0); - signal intTxReq : sl; - signal intTxIdle : sl; + signal vcInFrame : slv(3 downto 0) := (others => '0'); + signal intTxReq : sl := '0'; + signal intTxIdle : sl := '0'; signal nxtTxReq : sl; signal nxtTxIdle : sl; signal nxtTxTimeout : sl; - signal intTxTimeout : sl; - signal vcTimerA : slv(23 downto 0); - signal vcTimerB : slv(23 downto 0); - signal vcTimerC : slv(23 downto 0); - signal vcTimerD : slv(23 downto 0); - signal vcTimeout : slv(3 downto 0); + signal intTxTimeout : sl := '0'; + signal vcTimerA : slv(23 downto 0) := (others => '0'); + signal vcTimerB : slv(23 downto 0) := (others => '0'); + signal vcTimerC : slv(23 downto 0) := (others => '0'); + signal vcTimerD : slv(23 downto 0) := (others => '0'); + signal vcTimeout : slv(3 downto 0) := (others => '0'); signal gateTxValid : slv(3 downto 0); -- Schedular state @@ -98,7 +98,7 @@ architecture Pgp2bTxSched of Pgp2bTxSched is constant ST_GAP_A_C : slv(2 downto 0) := "100"; constant ST_GAP_B_C : slv(2 downto 0) := "101"; constant ST_GAP_C_C : slv(2 downto 0) := "110"; - signal curState : slv(2 downto 0); + signal curState : slv(2 downto 0) := ST_ARB_C; signal nxtState : slv(2 downto 0); begin From 1d900d3b0df5439460e266e678f95a8af14b9e75 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 21 Jul 2023 16:30:25 -0700 Subject: [PATCH 09/45] bug fix for out-of-bound SLV when (DATA_WIDTH_G <= 32) --- axi/axi-lite/rtl/AxiDualPortRam.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/axi/axi-lite/rtl/AxiDualPortRam.vhd b/axi/axi-lite/rtl/AxiDualPortRam.vhd index 6e50266ca0..60047b36d8 100644 --- a/axi/axi-lite/rtl/AxiDualPortRam.vhd +++ b/axi/axi-lite/rtl/AxiDualPortRam.vhd @@ -361,11 +361,11 @@ begin if (AXI_WR_EN_G) then v.axiAddr := axiWriteMaster.awaddr(AXI_RAM_ADDR_HIGH_C downto AXI_RAM_ADDR_LOW_C); if (DATA_WIDTH_G <= 32) then - decAddrInt := conv_integer(axiWriteMaster.awaddr(AXI_RAM_ADDR_LOW_C-1 downto 0)); + v.axiWrStrobe := axiWriteMaster.wstrb; else decAddrInt := conv_integer(axiWriteMaster.awaddr(AXI_DEC_ADDR_RANGE_C)); + v.axiWrStrobe((decAddrInt+1)*4-1 downto decAddrInt*4) := axiWriteMaster.wstrb; end if; - v.axiWrStrobe((decAddrInt+1)*4-1 downto decAddrInt*4) := axiWriteMaster.wstrb; end if; axiSlaveWriteResponse(v.axiWriteSlave, ite(AXI_WR_EN_G, AXI_RESP_OK_C, AXI_RESP_SLVERR_C)); -- Check for read transaction From 22b7416590042c07694c50c929a51e0fec908b06 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 21 Jul 2023 16:30:54 -0700 Subject: [PATCH 10/45] adding test_AxiLiteCrossbarTb.py --- axi/axi-lite/tb/AxiLiteCrossbarTb.vhd | 189 ++++++++++++++++++ tests/test_AxiLiteCrossbarTb.py | 266 ++++++++++++++++++++++++++ 2 files changed, 455 insertions(+) create mode 100644 axi/axi-lite/tb/AxiLiteCrossbarTb.vhd create mode 100644 tests/test_AxiLiteCrossbarTb.py diff --git a/axi/axi-lite/tb/AxiLiteCrossbarTb.vhd b/axi/axi-lite/tb/AxiLiteCrossbarTb.vhd new file mode 100644 index 0000000000..f897644063 --- /dev/null +++ b/axi/axi-lite/tb/AxiLiteCrossbarTb.vhd @@ -0,0 +1,189 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: surf.AxiLiteCrossbar cocoTB testbed +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; + +entity AxiLiteCrossbarTb is + port ( + -- AXI-Lite Interface + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(31 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(31 downto 0); + S_AXI_WSTRB : in std_logic_vector(3 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(31 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(31 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic); +end AxiLiteCrossbarTb; + +architecture mapping of AxiLiteCrossbarTb is + + constant NUM_AXIL_MASTERS_C : positive := 2; + + constant AXIL_XBAR_CONFIG_C : AxiLiteCrossbarMasterConfigArray(NUM_AXIL_MASTERS_C-1 downto 0) := genAxiLiteConfig(NUM_AXIL_MASTERS_C, x"0000_0000", 22, 20); + + constant NUM_CASCADE_MASTERS_C : positive := 2; + + constant CASCADE_XBAR_CONFIG_C : AxiLiteCrossbarMasterConfigArray(NUM_CASCADE_MASTERS_C-1 downto 0) := ( + 0 => ( + baseAddr => x"0010_2000", + addrBits => 12, + connectivity => X"0001"), + 1 => ( + baseAddr => x"0016_0000", + addrBits => 17, + connectivity => X"0001")); + + signal axilClk : sl; + signal axilRst : sl; + + signal axilReadMaster : AxiLiteReadMasterType; + signal axilReadSlave : AxiLiteReadSlaveType; + signal axilWriteMaster : AxiLiteWriteMasterType; + signal axilWriteSlave : AxiLiteWriteSlaveType; + + signal axilReadMasters : AxiLiteReadMasterArray(NUM_AXIL_MASTERS_C-1 downto 0); + signal axilReadSlaves : AxiLiteReadSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_DECERR_C); + signal axilWriteMasters : AxiLiteWriteMasterArray(NUM_AXIL_MASTERS_C-1 downto 0); + signal axilWriteSlaves : AxiLiteWriteSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C); + + signal cascadeReadMasters : AxiLiteReadMasterArray(NUM_CASCADE_MASTERS_C-1 downto 0); + signal cascadeReadSlaves : AxiLiteReadSlaveArray(NUM_CASCADE_MASTERS_C-1 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_DECERR_C); + signal cascadeWriteMasters : AxiLiteWriteMasterArray(NUM_CASCADE_MASTERS_C-1 downto 0); + signal cascadeWriteSlaves : AxiLiteWriteSlaveArray(NUM_CASCADE_MASTERS_C-1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C); + +begin + + U_ShimLayer : entity surf.SlaveAxiLiteIpIntegrator + generic map ( + EN_ERROR_RESP => true, + FREQ_HZ => 125000000, + ADDR_WIDTH => 32) + port map ( + -- IP Integrator AXI-Lite Interface + S_AXI_ACLK => S_AXI_ACLK, + S_AXI_ARESETN => S_AXI_ARESETN, + S_AXI_AWADDR => S_AXI_AWADDR, + S_AXI_AWPROT => S_AXI_AWPROT, + S_AXI_AWVALID => S_AXI_AWVALID, + S_AXI_AWREADY => S_AXI_AWREADY, + S_AXI_WDATA => S_AXI_WDATA, + S_AXI_WSTRB => S_AXI_WSTRB, + S_AXI_WVALID => S_AXI_WVALID, + S_AXI_WREADY => S_AXI_WREADY, + S_AXI_BRESP => S_AXI_BRESP, + S_AXI_BVALID => S_AXI_BVALID, + S_AXI_BREADY => S_AXI_BREADY, + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARPROT => S_AXI_ARPROT, + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_RREADY => S_AXI_RREADY, + -- SURF AXI-Lite Interface + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + + U_AXIL_XBAR : entity surf.AxiLiteCrossbar + generic map ( + NUM_SLAVE_SLOTS_G => 1, + NUM_MASTER_SLOTS_G => NUM_AXIL_MASTERS_C, + MASTERS_CONFIG_G => AXIL_XBAR_CONFIG_C) + port map ( + axiClk => axilClk, + axiClkRst => axilRst, + sAxiWriteMasters(0) => axilWriteMaster, + sAxiWriteSlaves(0) => axilWriteSlave, + sAxiReadMasters(0) => axilReadMaster, + sAxiReadSlaves(0) => axilReadSlave, + mAxiWriteMasters => axilWriteMasters, + mAxiWriteSlaves => axilWriteSlaves, + mAxiReadMasters => axilReadMasters, + mAxiReadSlaves => axilReadSlaves); + + U_MEM : entity surf.AxiDualPortRam + generic map ( + ADDR_WIDTH_G => 10, + DATA_WIDTH_G => 32) + port map ( + -- Axi Port + axiClk => axilClk, + axiRst => axilRst, + axiReadMaster => axilReadMasters(0), + axiReadSlave => axilReadSlaves(0), + axiWriteMaster => axilWriteMasters(0), + axiWriteSlave => axilWriteSlaves(0)); + + U_CASCADE_XBAR : entity surf.AxiLiteCrossbar + generic map ( + NUM_SLAVE_SLOTS_G => 1, + NUM_MASTER_SLOTS_G => NUM_CASCADE_MASTERS_C, + MASTERS_CONFIG_G => CASCADE_XBAR_CONFIG_C) + port map ( + axiClk => axilClk, + axiClkRst => axilRst, + sAxiWriteMasters(0) => axilWriteMasters(1), + sAxiWriteSlaves(0) => axilWriteSlaves(1), + sAxiReadMasters(0) => axilReadMasters(1), + sAxiReadSlaves(0) => axilReadSlaves(1), + mAxiWriteMasters => cascadeWriteMasters, + mAxiWriteSlaves => cascadeWriteSlaves, + mAxiReadMasters => cascadeReadMasters, + mAxiReadSlaves => cascadeReadSlaves); + + GEN_VEC : + for i in NUM_CASCADE_MASTERS_C-1 downto 0 generate + + U_MEM : entity surf.AxiDualPortRam + generic map ( + ADDR_WIDTH_G => 10, + DATA_WIDTH_G => 32) + port map ( + -- Axi Port + axiClk => axilClk, + axiRst => axilRst, + axiReadMaster => cascadeReadMasters(i), + axiReadSlave => cascadeReadSlaves(i), + axiWriteMaster => cascadeWriteMasters(i), + axiWriteSlave => cascadeWriteSlaves(i)); + + end generate GEN_VEC; + +end mapping; diff --git a/tests/test_AxiLiteCrossbarTb.py b/tests/test_AxiLiteCrossbarTb.py new file mode 100644 index 0000000000..779508723d --- /dev/null +++ b/tests/test_AxiLiteCrossbarTb.py @@ -0,0 +1,266 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# dut_tb +import itertools +import logging +import os +import random + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotb.regression import TestFactory + +from cocotbext.axi import AxiLiteBus, AxiLiteMaster + +# test_AxiLiteCrossbarTb +from cocotb_test.simulator import run +import pytest +import glob +import os + +class TB: + def __init__(self, dut): + + # Pointer to DUT object + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + # Start clock (125 MHz) in a separate thread + cocotb.start_soon(Clock(dut.S_AXI_ACLK, 8.0, units='ns').start()) + + # Create the AXI-Lite Master + self.axil_master = AxiLiteMaster( + bus = AxiLiteBus.from_prefix(dut, 'S_AXI'), + clock = dut.S_AXI_ACLK, + reset = dut.S_AXI_ARESETN, + reset_active_level=False) + + def set_idle_generator(self, generator=None): + if generator: + self.axil_master.write_if.aw_channel.set_pause_generator(generator()) + self.axil_master.write_if.w_channel.set_pause_generator(generator()) + self.axil_master.read_if.ar_channel.set_pause_generator(generator()) + + def set_backpressure_generator(self, generator=None): + if generator: + self.axil_master.write_if.b_channel.set_pause_generator(generator()) + self.axil_master.read_if.r_channel.set_pause_generator(generator()) + + async def cycle_reset(self): + self.dut.S_AXI_ARESETN.setimmediatevalue(0) + await RisingEdge(self.dut.S_AXI_ACLK) + await RisingEdge(self.dut.S_AXI_ACLK) + self.dut.S_AXI_ARESETN.value = 0 + await RisingEdge(self.dut.S_AXI_ACLK) + await RisingEdge(self.dut.S_AXI_ACLK) + self.dut.S_AXI_ARESETN.value = 1 + await RisingEdge(self.dut.S_AXI_ACLK) + await RisingEdge(self.dut.S_AXI_ACLK) + +async def run_test_bytes(dut, data_in=None, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + byte_lanes = tb.axil_master.write_if.byte_lanes + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + for length in range(1, byte_lanes*2): + for memDev in [0x0000_0000,0x0010_2000,0x0016_0000]: + for offset in range(byte_lanes): + addr = offset+memDev + tb.log.info( f'length={length},addr={hex(addr)}' ) + test_data = bytearray([x % 256 for x in range(length)]) + await tb.axil_master.write(addr, test_data) + data = await tb.axil_master.read(addr, length) + + await RisingEdge(dut.S_AXI_ACLK) + await RisingEdge(dut.S_AXI_ACLK) + + +async def run_test_words(dut): + + tb = TB(dut) + + byte_lanes = tb.axil_master.write_if.byte_lanes + + await tb.cycle_reset() + + for length in list(range(1, 4)): + for memDev in [0x0000_0000,0x0010_2000,0x0016_0000]: + for offset in list(range(byte_lanes)): + addr = offset + tb.log.info( f'length={length},addr={hex(addr)}' ) + + test_data = bytearray([x % 256 for x in range(length)]) + event = tb.axil_master.init_write(addr, test_data) + await event.wait() + event = tb.axil_master.init_read(addr, length) + await event.wait() + assert event.data.data == test_data + + test_data = bytearray([x % 256 for x in range(length)]) + await tb.axil_master.write(addr, test_data) + assert (await tb.axil_master.read(addr, length)).data == test_data + + test_data = [x * 0x1001 for x in range(length)] + await tb.axil_master.write_words(addr, test_data) + assert await tb.axil_master.read_words(addr, length) == test_data + + test_data = [x * 0x10200201 for x in range(length)] + await tb.axil_master.write_dwords(addr, test_data) + assert await tb.axil_master.read_dwords(addr, length) == test_data + + test_data = [x * 0x1020304004030201 for x in range(length)] + await tb.axil_master.write_qwords(addr, test_data) + assert await tb.axil_master.read_qwords(addr, length) == test_data + + test_data = 0x01*length + await tb.axil_master.write_byte(addr, test_data) + assert await tb.axil_master.read_byte(addr) == test_data + + test_data = 0x1001*length + await tb.axil_master.write_word(addr, test_data) + assert await tb.axil_master.read_word(addr) == test_data + + test_data = 0x10200201*length + await tb.axil_master.write_dword(addr, test_data) + assert await tb.axil_master.read_dword(addr) == test_data + + test_data = 0x1020304004030201*length + await tb.axil_master.write_qword(addr, test_data) + assert await tb.axil_master.read_qword(addr) == test_data + + await RisingEdge(dut.S_AXI_ACLK) + await RisingEdge(dut.S_AXI_ACLK) + +async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + async def worker(master, offset, aperture, count=16): + for k in range(count): + length = random.randint(1, min(32, aperture)) + addr = offset+random.randint(0, aperture-length) + test_data = bytearray([x % 256 for x in range(length)]) + + await Timer(random.randint(1, 100), 'ns') + + await master.write(addr, test_data) + + await Timer(random.randint(1, 100), 'ns') + + data = await master.read(addr, length) + assert data.data == test_data + + workers = [] + + for k in [0x0000_0000,0x0010_2000,0x0016_0000]: + workers.append(cocotb.start_soon(worker(tb.axil_master, k, 0x1000, count=16))) + + while workers: + await workers.pop(0).join() + + await RisingEdge(dut.S_AXI_ACLK) + await RisingEdge(dut.S_AXI_ACLK) + + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +if cocotb.SIM_NAME: + + ################# + # run_test_bytes + ################# + factory = TestFactory(run_test_bytes) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.generate_tests() + + ################# + # run_test_words + ################# + factory = TestFactory(run_test_words) + factory.generate_tests() + + ################# + # run_stress_test + ################# + factory = TestFactory(run_stress_test) + factory.generate_tests() + +tests_dir = os.path.dirname(__file__) +tests_module = 'AxiLiteCrossbarTb' + +############################################################################## + +@pytest.mark.parametrize( + "parameters", [ + None + ]) +def test_AxiLiteCrossbarTb(parameters): + + # https://github.com/themperek/cocotb-test#arguments-for-simulatorrun + # https://github.com/themperek/cocotb-test/blob/master/cocotb_test/simulator.py + run( + # top level HDL + toplevel = f'surf.{tests_module}'.lower(), + + # name of the file that contains @cocotb.test() -- this file + # https://docs.cocotb.org/en/stable/building.html?#envvar-MODULE + module = f'test_{tests_module}', + + # https://docs.cocotb.org/en/stable/building.html?#var-TOPLEVEL_LANG + toplevel_lang = 'vhdl', + + # VHDL source files to include. + # Can be specified as a list or as a dict of lists with the library name as key, + # if the simulator supports named libraries. + vhdl_sources = { + 'surf' : glob.glob(f'{tests_dir}/../build/SRC_VHDL/surf/*'), + 'ruckus' : glob.glob(f'{tests_dir}/../build/SRC_VHDL/ruckus/*'), + }, + + # A dictionary of top-level parameters/generics. + parameters = parameters, + + # The directory used to compile the tests. (default: sim_build) + sim_build = f'{tests_dir}/sim_build/{tests_module}', + + # A dictionary of extra environment variables set in simulator process. + extra_env=parameters, + + # Select a simulator + simulator="ghdl", + + # use of synopsys package "std_logic_arith" needs the -fsynopsys option + # -frelaxed-rules option to allow IP integrator attributes + # When two operators are overloaded, give preference to the explicit declaration (-fexplicit) + vhdl_compile_args = ['-fsynopsys','-frelaxed-rules', '-fexplicit'], + + ######################################################################## + # Dump waveform to file ($ gtkwave sim_build/path/To/{tests_module}.ghw) + ######################################################################## + # sim_args =[f'--wave={tests_module}.ghw'], + ) From 89f050b7fe3bd328eff93f88caae1b190a36ad2e Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 21 Jul 2023 16:37:34 -0700 Subject: [PATCH 11/45] linter fix --- tests/test_AxiLiteCrossbarTb.py | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/tests/test_AxiLiteCrossbarTb.py b/tests/test_AxiLiteCrossbarTb.py index 779508723d..03d9a5e950 100644 --- a/tests/test_AxiLiteCrossbarTb.py +++ b/tests/test_AxiLiteCrossbarTb.py @@ -8,12 +8,6 @@ ## the terms contained in the LICENSE.txt file. ############################################################################## -# dut_tb -import itertools -import logging -import os -import random - import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge, Timer @@ -26,6 +20,9 @@ import pytest import glob import os +import itertools +import logging +import random class TB: def __init__(self, dut): @@ -87,6 +84,7 @@ async def run_test_bytes(dut, data_in=None, idle_inserter=None, backpressure_ins test_data = bytearray([x % 256 for x in range(length)]) await tb.axil_master.write(addr, test_data) data = await tb.axil_master.read(addr, length) + assert data.data == test_data await RisingEdge(dut.S_AXI_ACLK) await RisingEdge(dut.S_AXI_ACLK) From b4a2ffbccc223a3bb3ea3fd043219a14fda84dd5 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 21 Jul 2023 16:58:10 -0700 Subject: [PATCH 12/45] Revert to previous refresh rate --- protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd index 3602ecd79c..42602b5c9e 100644 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd @@ -319,7 +319,7 @@ begin generic map ( TPD_G => TPD_G, REF_CLK_FREQ_G => AXI_CLK_FREQ_G, - REFRESH_RATE_G => 1000.0, + REFRESH_RATE_G => 100.0, CLK_LOWER_LIMIT_G => 155.0E+6, CLK_UPPER_LIMIT_G => 158.0E+6, CNT_WIDTH_G => 32) @@ -434,7 +434,7 @@ begin generic map ( TPD_G => TPD_G, REF_CLK_FREQ_G => AXI_CLK_FREQ_G, - REFRESH_RATE_G => 1000.0, + REFRESH_RATE_G => 100.0, CLK_LOWER_LIMIT_G => 155.0E+6, CLK_UPPER_LIMIT_G => 158.0E+6, CNT_WIDTH_G => 32) From cfbb703adc7684224d32f7d3635f8feabf523221 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 31 Jul 2023 15:51:08 -0700 Subject: [PATCH 13/45] Fix for rogue v6 compatibility --- python/surf/devices/microchip/_Axi24LC64FT.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/python/surf/devices/microchip/_Axi24LC64FT.py b/python/surf/devices/microchip/_Axi24LC64FT.py index 5d66a39306..c9fc0b53b3 100644 --- a/python/surf/devices/microchip/_Axi24LC64FT.py +++ b/python/surf/devices/microchip/_Axi24LC64FT.py @@ -31,7 +31,7 @@ def __init__(self, self.add(pr.RemoteVariable( name = "Mem", description = "Memory Array", - size = (4*nelms), + offset = 0x0000, numValues = nelms, valueBits = 32, valueStride = 32, From f36227bf9c0e3057f130d115df7db9eb73e02188 Mon Sep 17 00:00:00 2001 From: Julian Mendez Date: Tue, 8 Aug 2023 14:58:48 -0700 Subject: [PATCH 14/45] fix idelaye3 issues - busy signal and placement --- xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd | 2 +- xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd b/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd index 3f7f95b18c..e63f22b401 100644 --- a/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd +++ b/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd @@ -134,7 +134,7 @@ begin -- Outputs patchLoad <= r.Load; patchCntValue <= r.dlyValue; - if (v.dlyTarget /= CNTVALUEOUT) or (r.state /= IDLE_S) then + if (r.state /= IDLE_S) then busy <= '1'; else busy <= '0'; diff --git a/xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd b/xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd index f8304daa25..06e93d2fec 100644 --- a/xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd +++ b/xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd @@ -37,7 +37,8 @@ entity Idelaye3Wrapper is IS_RST_INVERTED : bit := '0'; -- Optional inversion for RST REFCLK_FREQUENCY : real := 300.0; -- IDELAYCTRL clock input frequency in MHz (200.0-2667.0) SIM_DEVICE : string := "ULTRASCALE"; -- Set the device version (ULTRASCALE, ULTRASCALE_PLUS) - UPDATE_MODE : string := "ASYNC"); -- Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC) + UPDATE_MODE : string := "ASYNC"; + IODELAY_GROUP_G : string := "DLYGRP_C"); -- Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC) port ( BUSY : out sl; -- 1-bit output: Patch module is busy CASC_OUT : out sl; -- 1-bit output: Cascade delay output to ODELAY input cascade @@ -62,6 +63,9 @@ architecture rtl of Idelaye3Wrapper is signal patchCntValue : slv(8 downto 0); signal patchLoad : sl; + attribute IODELAY_GROUP : string; + attribute IODELAY_GROUP of U_IDELAYE3 : label is IODELAY_GROUP_G; + begin CNTVALUEOUT <= currentCntValue; From 401dd92b213ae3ea46a74de31cf8c6e834a3c6cb Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 21 Aug 2023 12:12:04 -0700 Subject: [PATCH 15/45] adding AxiStreamConcat.vhd --- axi/axi-stream/rtl/AxiStreamConcat.vhd | 351 +++++++++++++++++++++++++ 1 file changed, 351 insertions(+) create mode 100644 axi/axi-stream/rtl/AxiStreamConcat.vhd diff --git a/axi/axi-stream/rtl/AxiStreamConcat.vhd b/axi/axi-stream/rtl/AxiStreamConcat.vhd new file mode 100644 index 0000000000..f09db376c7 --- /dev/null +++ b/axi/axi-stream/rtl/AxiStreamConcat.vhd @@ -0,0 +1,351 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Firmware module that AxiStreamConcat multiple AXI stream frames +-- together. It will ignore TKEEP and the format of the frame. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.SsiPkg.all; + +entity AxiStreamConcat is + generic ( + TPD_G : time := 1 ns; + MAX_NUMBER_SUB_FRAMES_G : positive := 32; -- Units of sub-frames + SUPER_FRAME_BYTE_THRESHOLD_G : natural := 8192; -- Units of bytes + MAX_CLK_GAP_G : natural := 256; -- Units of clock cycles + AXIS_CONFIG_G : AxiStreamConfigType; + INPUT_PIPE_STAGES_G : natural := 0; + OUTPUT_PIPE_STAGES_G : natural := 1); + port ( + -- Clock and Reset + axisClk : in sl; + axisRst : in sl; + -- External Control Interface + forceTerm : in sl := '0'; + superFrameByteThreshold : in slv(31 downto 0) := toSlv(SUPER_FRAME_BYTE_THRESHOLD_G, 32); + maxSubFrames : in slv(15 downto 0) := toSlv(MAX_NUMBER_SUB_FRAMES_G, 16); + maxClkGap : in slv(31 downto 0) := toSlv(MAX_CLK_GAP_G, 32); + idle : out sl; + -- AXIS Interfaces + sAxisMaster : in AxiStreamMasterType; + sAxisSlave : out AxiStreamSlaveType; + mAxisMaster : out AxiStreamMasterType; + mAxisSlave : in AxiStreamSlaveType); +end entity AxiStreamConcat; + +architecture rtl of AxiStreamConcat is + + constant AXIS_WORD_SIZE_C : positive := AXIS_CONFIG_G.TDATA_BYTES_C; -- Units of bytes + + constant WIDTH_C : slv(3 downto 0) := toSlv(log2(AXIS_WORD_SIZE_C/2), 4); + + type StateType is ( + IDLE_S, + SUB_FRAME_S, + TAIL_S, + GAP_S); + + type RegType is record + superFrameByteThreshold : slv(31 downto 0); + superByteCnt : slv(31 downto 0); + subByteCnt : slv(31 downto 0); + maxSubFrames : slv(15 downto 0); + subFrameCnt : slv(15 downto 0); + maxClkGap : slv(31 downto 0); + clkGapCnt : slv(31 downto 0); + superFrameByteThresholdDet : sl; + maxSubFramesDet : sl; + forceTerm : sl; + sof : sl; + seqCnt : slv(7 downto 0); + tDest : slv(7 downto 0); + tUserFirst : slv(7 downto 0); + tUserLast : slv(7 downto 0); + chunkCnt : natural range 0 to 3; + rxSlave : AxiStreamSlaveType; + txMaster : AxiStreamMasterType; + state : StateType; + end record RegType; + + constant REG_INIT_C : RegType := ( + superFrameByteThreshold => toSlv(SUPER_FRAME_BYTE_THRESHOLD_G, 32), + superByteCnt => toSlv(AXIS_WORD_SIZE_C, 32), + subByteCnt => (others => '0'), + maxSubFrames => toSlv(MAX_NUMBER_SUB_FRAMES_G, 16), + subFrameCnt => (others => '0'), + maxClkGap => toSlv(MAX_CLK_GAP_G, 32), + clkGapCnt => (others => '0'), + superFrameByteThresholdDet => '0', + maxSubFramesDet => '0', + forceTerm => '0', + sof => '1', + seqCnt => (others => '0'), + tDest => (others => '0'), + tUserFirst => (others => '0'), + tUserLast => (others => '0'), + chunkCnt => 1, + rxSlave => AXI_STREAM_SLAVE_INIT_C, + txMaster => AXI_STREAM_MASTER_INIT_C, + state => HEADER_S); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal rxMaster : AxiStreamMasterType; + signal rxSlave : AxiStreamSlaveType; + signal txMaster : AxiStreamMasterType; + signal txSlave : AxiStreamSlaveType; + +begin + + ----------------- + -- Input pipeline + ----------------- + U_Input : entity surf.AxiStreamPipeline + generic map ( + TPD_G => TPD_G, + PIPE_STAGES_G => INPUT_PIPE_STAGES_G) + port map ( + axisClk => axisClk, + axisRst => axisRst, + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + mAxisMaster => rxMaster, + mAxisSlave => rxSlave); + + comb : process (axisRst, forceTerm, maxClkGap, maxSubFrames, r, rxMaster, + superFrameByteThreshold, txSlave) is + variable v : RegType; + + procedure doTail is + begin + -- Check for end of super-frame condition + if (v.superFrameByteThresholdDet = '1') or (v.maxSubFramesDet = '1') or (v.forceTerm = '1') then + -- Move the outbound data + v.txMaster.tValid := '1'; + -- Terminate the super-frame + v.txMaster.tLast := '1'; + -- Set EOFE + ssiSetUserEofe(AXIS_CONFIG_G, v.txMaster, v.forceTerm); + -- Next state + v.state := IDLE_S; + -- Check if new data to move or bypassing clock gap + elsif (rxMaster.tValid = '1') or (r.maxClkGap = 0) then + -- Move the outbound data + v.txMaster.tValid := '1'; + -- Next state + v.state := SUB_FRAME_S; + else + -- Next state + v.state := GAP_S; + end if; + end procedure doTail; + + begin + -- Latch the current value + v := r; + + -- Reset the strobes + v.rxSlave.tReady := r.forceTerm; + if (txSlave.tReady = '1') then + v.txMaster.tValid := '0'; + v.txMaster.tLast := '0'; + v.txMaster.tUser := (others => '0'); + end if; + + -- Check for max. super frame + if(r.superByteCnt = r.superFrameByteThreshold) and (r.superFrameByteThreshold /= 0) then + -- Set the flag + v.superFrameByteThresholdDet := '1'; + end if; + + -- Check for max. super frame + if(r.subFrameCnt = r.maxSubFrames) then + -- Set the flag + v.maxSubFramesDet := '1'; + end if; + + -- Register the value + v.forceTerm := forceTerm; + + -- Main state machine + case r.state is + ---------------------------------------------------------------------- + when IDLE_S => + -- Reset the flag + v.superFrameByteThresholdDet := '0'; + v.maxSubFramesDet := '0'; + v.sof := '0'; + -- Sample external signals + v.superFrameByteThreshold := superFrameByteThreshold; + v.maxSubFrames := maxSubFrames; + v.maxClkGap := maxClkGap; + -- Floor the superFrameByteThreshold to nearest word increment + -- This is done to remove the ">" operator + v.superFrameByteThreshold(bitSize(AXIS_WORD_SIZE_C)-1 downto 0) := (others => '0'); + -- Check for zero byte superFrameByteThreshold case and not using a zero value external threshold + if (v.superFrameByteThreshold = 0) and (superFrameByteThreshold /= 0) then + -- Prevent zero case + v.superFrameByteThreshold := toSlv(AXIS_WORD_SIZE_C, 32); + end if; + -- Check for zero maxSubFrames case + if (v.maxSubFrames = 0) then + -- Prevent zero case + v.maxSubFrames := toSlv(1, 16); + end if; + -- Check if ready to move data + if (rxMaster.tValid = '1') and (r.forceTerm = '0') then + -- Next state + v.state := SUB_FRAME_S; + end if; + -- Reset the counters + v.subFrameCnt := (others => '0'); + v.superByteCnt := (others => '0'); + ---------------------------------------------------------------------- + when SUB_FRAME_S => + -- Check if ready to move data + if (rxMaster.tValid = '1') and (v.txMaster.tValid = '0') then + -- Accept the inbound data + v.rxSlave.tReady := '1'; + -- Move the outbound data + v.txMaster.tValid := '1'; + v.txMaster.tData := rxMaster.tData; + -- Check SOF + if (r.sof = '1') then + -- Set the SOF bit + ssiSetUserSof(AXIS_CONFIG_G, v.txMaster, '1'); + -- Clear the flag + v.sof := '0'; + end if; + -- Check if first transaction + if (r.subByteCnt = 0) then + -- Sample the first transaction + v.tUserFirst(AXIS_CONFIG_G.TUSER_BITS_C-1 downto 0) := axiStreamGetUserField(AXIS_CONFIG_G, rxMaster, 0); + -- Increment the sub-frame counter + v.subFrameCnt := r.subFrameCnt + 1; + end if; + -- Check for last transaction in sub-frame + if (rxMaster.tLast = '1') then + -- Hold off on the write + v.txMaster.tValid := '0'; + -- Increment the sub-frame byte counter + v.subByteCnt := r.subByteCnt + getTKeep(rxMaster.tKeep, AXIS_CONFIG_G); + -- Sample the meta data + v.tUserLast(AXIS_CONFIG_G.TUSER_BITS_C-1 downto 0) := axiStreamGetUserField(AXIS_CONFIG_G, rxMaster); + v.tDest(AXIS_CONFIG_G.TDEST_BITS_C-1 downto 0) := rxMaster.tDest(AXIS_CONFIG_G.TDEST_BITS_C-1 downto 0); + -- Next state + v.state := TAIL_S; + else + -- Increment the sub-frame byte counter + v.subByteCnt := r.subByteCnt + AXIS_WORD_SIZE_C; + end if; + -- Increment the super-frame byte counter + v.superByteCnt := r.superByteCnt + AXIS_WORD_SIZE_C; + end if; + ---------------------------------------------------------------------- + when TAIL_S => + -- Reset the counter + v.subByteCnt := (others => '0'); + -- Process the tail + doTail; + -- Preset chunk counter + v.chunkCnt := 1; + -- Increment the super-frame byte counter + v.superByteCnt := r.superByteCnt + AXIS_WORD_SIZE_C; + ---------------------------------------------------------------------- + when GAP_S => + -- Check for new sub-frame + if (rxMaster.tValid = '1') then + -- Reset the counter + v.clkGapCnt := (others => '0'); + -- Move the data + v.txMaster.tValid := '1'; + -- Next state + v.state := SUB_FRAME_S; + -- Check for the clock gap event + elsif (r.clkGapCnt = r.maxClkGap) then + -- Check if ready to move data + if (v.txMaster.tValid = '0') then + -- Reset the counter + v.clkGapCnt := (others => '0'); + -- Move the outbound data + v.txMaster.tValid := '1'; + -- Terminate the super-frame + v.txMaster.tLast := '1'; + -- Next state + v.state := IDLE_S; + end if; + else + -- Increment the counter + v.clkGapCnt := r.clkGapCnt + 1; + end if; + ---------------------------------------------------------------------- + end case; + + -- Check for force termination + if (r.forceTerm = '1') and (r.state /= IDLE_S) then + doTail; + end if; + + -- Always the same outbound AXIS stream width + v.txMaster.tKeep := genTKeep(AXIS_WORD_SIZE_C); + v.txMaster.tStrb := genTKeep(AXIS_WORD_SIZE_C); + + -- Outputs + rxSlave <= v.rxSlave; + txMaster <= r.txMaster; + if (r.state = IDLE_S) then + idle <= '1'; + else + idle <= '0'; + end if; + + -- Reset + if (axisRst = '1') then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + end process comb; + + seq : process (axisClk) is + begin + if (rising_edge(axisClk)) then + r <= rin after TPD_G; + end if; + end process seq; + + ------------------ + -- Output pipeline + ------------------ + U_Output : entity surf.AxiStreamPipeline + generic map ( + TPD_G => TPD_G, + PIPE_STAGES_G => OUTPUT_PIPE_STAGES_G) + port map ( + axisClk => axisClk, + axisRst => axisRst, + sAxisMaster => txMaster, + sAxisSlave => txSlave, + mAxisMaster => mAxisMaster, + mAxisSlave => mAxisSlave); + +end rtl; From 8dc7775bb26b953c9e872554e98f6bc9c58bd459 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 28 Aug 2023 11:58:36 -0700 Subject: [PATCH 16/45] expanding VauxpVauxn into an array --- python/surf/xilinx/_AxiSysMonUltraScale.py | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/python/surf/xilinx/_AxiSysMonUltraScale.py b/python/surf/xilinx/_AxiSysMonUltraScale.py index 0fda8f50ff..26f04698cb 100644 --- a/python/surf/xilinx/_AxiSysMonUltraScale.py +++ b/python/surf/xilinx/_AxiSysMonUltraScale.py @@ -236,16 +236,17 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll description = "Gain Offset", ) - addPair( - name = 'VauxpVauxn', - offset = 0x440, - bitSize = 12, - bitOffset = 4, - units = "V", - function = self.convAuxVoltage, - pollInterval = 5, - description = "VAUXP_VAUXN's ADC values", - ) + for i in range(16): + addPair( + name = f'VauxpVauxn[{i}]', + offset = 0x440+(4*i), + bitSize = 12, + bitOffset = 4, + units = "V", + function = self.convAuxVoltage, + pollInterval = 5, + description = "VAUXP_VAUXN's ADC values", + ) addPair( name = 'MaxTemperature', From 0c2c4d67536055cbf2093a6aee7f2411cc14ebc0 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 28 Aug 2023 12:01:38 -0700 Subject: [PATCH 17/45] adding pollInterval to arg --- python/surf/xilinx/_AxiSysMonUltraScale.py | 39 +++++++++++----------- 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/python/surf/xilinx/_AxiSysMonUltraScale.py b/python/surf/xilinx/_AxiSysMonUltraScale.py index 26f04698cb..109c817cda 100644 --- a/python/surf/xilinx/_AxiSysMonUltraScale.py +++ b/python/surf/xilinx/_AxiSysMonUltraScale.py @@ -16,6 +16,7 @@ def __init__( description = "AXI-Lite System Managment for Xilinx Ultra Scale (Refer to PG185)", XIL_DEVICE_G = "ULTRASCALE", simpleViewList = ["Temperature", "VccInt", "VccAux", "VccBram"], + pollInterval = 5, **kwargs): super().__init__(description=description, **kwargs) @@ -133,7 +134,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "degC", function = self.convTemp, - pollInterval = 5, + pollInterval = pollInterval, description = "Temperature's ADC value", ) @@ -144,7 +145,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = "VCCINT's ADC value", ) @@ -155,7 +156,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = "VCCAUX's ADC value", ) @@ -166,7 +167,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convAuxVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = "VP/VN's ADC value", ) @@ -177,7 +178,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = "VREFP's ADC value", ) @@ -188,7 +189,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = "VREFN's ADC value", ) @@ -199,7 +200,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = "VBRAM's ADC value", ) @@ -210,7 +211,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = "Supply Offset", ) @@ -221,7 +222,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = "ADC Offset", ) @@ -232,7 +233,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = "Gain Offset", ) @@ -244,7 +245,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convAuxVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = "VAUXP_VAUXN's ADC values", ) @@ -255,7 +256,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "degC", function = self.convTemp, - pollInterval = 5, + pollInterval = pollInterval, description = "maximum temperature measurement", ) @@ -266,7 +267,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = "maximum VCCINT measurement", ) @@ -277,7 +278,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = "maximum VCCAUX measurement", ) @@ -288,7 +289,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = "maximum VBRAM measurement", ) @@ -299,7 +300,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "degC", function = self.convTemp, - pollInterval = 5, + pollInterval = pollInterval, description = "minimum temperature measurement", ) @@ -310,7 +311,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = "minimum VCCINT measurement", ) @@ -321,7 +322,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = "minimum VCCAUX measurement", ) @@ -332,7 +333,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = "minimum VBRAM measurement", ) From 3a1b85ca5bcef65edbfb698de32b3d397511c3aa Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 29 Aug 2023 09:52:39 -0700 Subject: [PATCH 18/45] bug fix for latest rogue --- python/surf/ethernet/udp/__init__.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/python/surf/ethernet/udp/__init__.py b/python/surf/ethernet/udp/__init__.py index 910c7db174..4cbef22f29 100644 --- a/python/surf/ethernet/udp/__init__.py +++ b/python/surf/ethernet/udp/__init__.py @@ -21,7 +21,7 @@ def getPortValue(var): def setPortValue(var, value, write): newValue = int.from_bytes(value.to_bytes(2, byteorder='little'), byteorder='big', signed=False) - var.dependencies[0].set(newValue,write) + var.dependencies[0].set(newValue, write=True) def getIpValue(var): x = var.dependencies[0].value() @@ -30,7 +30,7 @@ def getIpValue(var): def setIpValue(var, value, write): x = int(ipaddress.IPv4Address(value)) newValue = int.from_bytes(x.to_bytes(4, byteorder='little'), byteorder='big', signed=False) - var.dependencies[0].set(newValue,write) + var.dependencies[0].set(newValue, write=True) def getMacValue(var): x = var.dependencies[0].value() @@ -41,4 +41,4 @@ def setMacValue(var, value, write): if( len(x) == 6): x = [int(i,16) for i in x] newValue = ( '0x%02x%02x%02x%02x%02x%02x' % (x[5],x[4],x[3],x[2],x[1],x[0]) ) - var.dependencies[0].set(int(newValue,16),write) + var.dependencies[0].set(int(newValue,16), write=True) From a0dab8b7369ac7f207ed889a7e13b0616446a0be Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 29 Aug 2023 11:47:38 -0700 Subject: [PATCH 19/45] fixed typo --- python/surf/ethernet/udp/__init__.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/python/surf/ethernet/udp/__init__.py b/python/surf/ethernet/udp/__init__.py index 4cbef22f29..50e33da639 100644 --- a/python/surf/ethernet/udp/__init__.py +++ b/python/surf/ethernet/udp/__init__.py @@ -21,7 +21,7 @@ def getPortValue(var): def setPortValue(var, value, write): newValue = int.from_bytes(value.to_bytes(2, byteorder='little'), byteorder='big', signed=False) - var.dependencies[0].set(newValue, write=True) + var.dependencies[0].set(newValue, write=write) def getIpValue(var): x = var.dependencies[0].value() @@ -30,7 +30,7 @@ def getIpValue(var): def setIpValue(var, value, write): x = int(ipaddress.IPv4Address(value)) newValue = int.from_bytes(x.to_bytes(4, byteorder='little'), byteorder='big', signed=False) - var.dependencies[0].set(newValue, write=True) + var.dependencies[0].set(newValue, write=write) def getMacValue(var): x = var.dependencies[0].value() @@ -41,4 +41,4 @@ def setMacValue(var, value, write): if( len(x) == 6): x = [int(i,16) for i in x] newValue = ( '0x%02x%02x%02x%02x%02x%02x' % (x[5],x[4],x[3],x[2],x[1],x[0]) ) - var.dependencies[0].set(int(newValue,16), write=True) + var.dependencies[0].set(int(newValue,16), write=write) From d2df26856791d1e5b17a26d5df27f860d459b23e Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 31 Aug 2023 13:47:40 -0700 Subject: [PATCH 20/45] Add comments to document PRIORITY_G --- axi/axi-stream/rtl/AxiStreamMux.vhd | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/axi/axi-stream/rtl/AxiStreamMux.vhd b/axi/axi-stream/rtl/AxiStreamMux.vhd index ae533332a8..7a12f90d5a 100644 --- a/axi/axi-stream/rtl/AxiStreamMux.vhd +++ b/axi/axi-stream/rtl/AxiStreamMux.vhd @@ -43,6 +43,10 @@ entity AxiStreamMux is TID_MODE_G : string := "PASSTHROUGH"; -- In ROUTED mode, an array mapping how TID should be assigned for each slave port TID_ROUTES_G : Slv8Array := (0 => "--------"); + -- Assign a priority for each input stream index. + -- Higher priority streams will be selected over those with lower priority of both are active. + -- Format is (index => priority) + -- Leave unchanged for equal priority round-robbin PRIORITY_G : IntegerArray := (0 => 0); -- In INDEXED mode, assign slave index to TDEST at this bit offset TDEST_LOW_G : integer range 0 to 7 := 0; From d033f307cbce1e918bb9cb601545e323c5f01e8b Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 31 Aug 2023 13:48:47 -0700 Subject: [PATCH 21/45] Allow custom TDEST and TID on packetizer output stream --- protocols/packetizer/rtl/AxiStreamPacketizer2.vhd | 6 ++++-- protocols/packetizer/rtl/AxiStreamPacketizer2Pkg.vhd | 4 ++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/protocols/packetizer/rtl/AxiStreamPacketizer2.vhd b/protocols/packetizer/rtl/AxiStreamPacketizer2.vhd index 751f39ced9..38e248e63c 100644 --- a/protocols/packetizer/rtl/AxiStreamPacketizer2.vhd +++ b/protocols/packetizer/rtl/AxiStreamPacketizer2.vhd @@ -37,6 +37,8 @@ entity AxiStreamPacketizer2 is MAX_PACKET_BYTES_G : positive := 256*8; -- Must be a multiple of 8 SEQ_CNT_SIZE_G : positive range 4 to 16 := 16; TDEST_BITS_G : natural := 8; + OUTPUT_TDEST_G : slv(7 downto 0) := (others => '0'); + OUTPUT_TID_G : slv(7 downto 0) := (others => '0'); INPUT_PIPE_STAGES_G : natural := 0; OUTPUT_PIPE_STAGES_G : natural := 0); port ( @@ -384,8 +386,8 @@ begin -- Send data through v.outputAxisMaster := inputAxisMaster; v.outputAxisMaster.tUser := (others => '0'); - v.outputAxisMaster.tDest := (others => '0'); - v.outputAxisMaster.tId := (others => '0'); + v.outputAxisMaster.tDest := OUTPUT_TDEST_G; + v.outputAxisMaster.tId := OUTPUT_TID_G; -- Increment word count with each txn v.wordCount := r.wordCount + 1; diff --git a/protocols/packetizer/rtl/AxiStreamPacketizer2Pkg.vhd b/protocols/packetizer/rtl/AxiStreamPacketizer2Pkg.vhd index 3ff0c7956e..c037010a94 100644 --- a/protocols/packetizer/rtl/AxiStreamPacketizer2Pkg.vhd +++ b/protocols/packetizer/rtl/AxiStreamPacketizer2Pkg.vhd @@ -60,8 +60,8 @@ package AxiStreamPacketizer2Pkg is constant PACKETIZER2_AXIS_CFG_C : AxiStreamConfigType := ( TSTRB_EN_C => false, TDATA_BYTES_C => 8, - TDEST_BITS_C => 0, - TID_BITS_C => 0, + TDEST_BITS_C => 8, + TID_BITS_C => 8, TKEEP_MODE_C => TKEEP_NORMAL_C, TUSER_BITS_C => 2, TUSER_MODE_C => TUSER_FIRST_LAST_C); From 166832ae1d0b6f354b5d0db7c8ad48e44ce49e3f Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 1 Sep 2023 08:26:56 -0700 Subject: [PATCH 22/45] bug fix for xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd --- xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd b/xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd index a5d4c8ef5a..a775879473 100644 --- a/xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd +++ b/xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd @@ -332,7 +332,7 @@ begin end generate; FbNoBufg : if (not FB_BUFG_G) generate - clkFbOut <= clkFbIn; + clkFbIn <= clkFbOut; end generate; ClkOutGen : for i in NUM_CLOCKS_G-1 downto 0 generate From b8f69101f7174afbeb54c05d01cf51bc1d8195bd Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 1 Sep 2023 08:31:59 -0700 Subject: [PATCH 23/45] (bulkOpEn=False) FALSE for large variables --- python/surf/devices/microchip/_Axi24LC64FT.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/python/surf/devices/microchip/_Axi24LC64FT.py b/python/surf/devices/microchip/_Axi24LC64FT.py index c9fc0b53b3..61ae10f49c 100644 --- a/python/surf/devices/microchip/_Axi24LC64FT.py +++ b/python/surf/devices/microchip/_Axi24LC64FT.py @@ -36,5 +36,5 @@ def __init__(self, valueBits = 32, valueStride = 32, bitSize = 32 * nelms, - # mode = "RO", + bulkOpEn = False, # FALSE for large variables, )) From abc065797ab818304241a94fcf01d69fc11dcd2a Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 1 Sep 2023 08:48:57 -0700 Subject: [PATCH 24/45] NOT start with the simpleView --- python/surf/xilinx/_AxiSysMonUltraScale.py | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/python/surf/xilinx/_AxiSysMonUltraScale.py b/python/surf/xilinx/_AxiSysMonUltraScale.py index 109c817cda..c2de0bf748 100644 --- a/python/surf/xilinx/_AxiSysMonUltraScale.py +++ b/python/surf/xilinx/_AxiSysMonUltraScale.py @@ -15,7 +15,7 @@ def __init__( self, description = "AXI-Lite System Managment for Xilinx Ultra Scale (Refer to PG185)", XIL_DEVICE_G = "ULTRASCALE", - simpleViewList = ["Temperature", "VccInt", "VccAux", "VccBram"], + simpleViewList = None, pollInterval = 5, **kwargs): super().__init__(description=description, **kwargs) @@ -568,8 +568,9 @@ def convAuxVoltage(var): return round(var.dependencies[0].value() * 244e-6,3) def simpleView(self): - # Hide all the variable - self.hideVariables(hidden=True) - # Then unhide the most interesting ones - vars = self.simpleViewList - self.hideVariables(hidden=False, variables=vars) + if self.simpleViewList is not None: + # Hide all the variable + self.hideVariables(hidden=True) + # Then unhide the most interesting ones + vars = self.simpleViewList + self.hideVariables(hidden=False, variables=vars) From 9aee90027c62f2e35424401b079f6167346e229b Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 1 Sep 2023 09:20:01 -0700 Subject: [PATCH 25/45] fixed REG_INIT_C syntax bug and general clean up --- axi/axi-stream/rtl/AxiStreamConcat.vhd | 27 +++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/axi/axi-stream/rtl/AxiStreamConcat.vhd b/axi/axi-stream/rtl/AxiStreamConcat.vhd index f09db376c7..c2717e5afd 100644 --- a/axi/axi-stream/rtl/AxiStreamConcat.vhd +++ b/axi/axi-stream/rtl/AxiStreamConcat.vhd @@ -4,6 +4,15 @@ -- Description: Firmware module that AxiStreamConcat multiple AXI stream frames -- together. It will ignore TKEEP and the format of the frame. ------------------------------------------------------------------------------- +-- Note: This module is similiar to "AxiStreamBatcher.vhd" but does NOT +-- have the following features +-- 1) No super header +-- 2) No tail footer +-- 3) Only supports TKEEP_FIXED_C +-- Because of these limitations, it is important to encode the user +-- metadata into payload. Use AxiStreamBatcher instead if you need +-- a generalized batcher +------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the -- top-level directory of this distribution and at: @@ -58,7 +67,7 @@ architecture rtl of AxiStreamConcat is type StateType is ( IDLE_S, SUB_FRAME_S, - TAIL_S, + EOF_CHECK_S, GAP_S); type RegType is record @@ -102,7 +111,7 @@ architecture rtl of AxiStreamConcat is chunkCnt => 1, rxSlave => AXI_STREAM_SLAVE_INIT_C, txMaster => AXI_STREAM_MASTER_INIT_C, - state => HEADER_S); + state => IDLE_S); signal r : RegType := REG_INIT_C; signal rin : RegType; @@ -133,7 +142,7 @@ begin superFrameByteThreshold, txSlave) is variable v : RegType; - procedure doTail is + procedure doEofCheck is begin -- Check for end of super-frame condition if (v.superFrameByteThresholdDet = '1') or (v.maxSubFramesDet = '1') or (v.forceTerm = '1') then @@ -155,7 +164,7 @@ begin -- Next state v.state := GAP_S; end if; - end procedure doTail; + end procedure doEofCheck; begin -- Latch the current value @@ -250,7 +259,7 @@ begin v.tUserLast(AXIS_CONFIG_G.TUSER_BITS_C-1 downto 0) := axiStreamGetUserField(AXIS_CONFIG_G, rxMaster); v.tDest(AXIS_CONFIG_G.TDEST_BITS_C-1 downto 0) := rxMaster.tDest(AXIS_CONFIG_G.TDEST_BITS_C-1 downto 0); -- Next state - v.state := TAIL_S; + v.state := EOF_CHECK_S; else -- Increment the sub-frame byte counter v.subByteCnt := r.subByteCnt + AXIS_WORD_SIZE_C; @@ -259,11 +268,11 @@ begin v.superByteCnt := r.superByteCnt + AXIS_WORD_SIZE_C; end if; ---------------------------------------------------------------------- - when TAIL_S => + when EOF_CHECK_S => -- Reset the counter v.subByteCnt := (others => '0'); - -- Process the tail - doTail; + -- Check for EOF (TLAST) + doEofCheck; -- Preset chunk counter v.chunkCnt := 1; -- Increment the super-frame byte counter @@ -300,7 +309,7 @@ begin -- Check for force termination if (r.forceTerm = '1') and (r.state /= IDLE_S) then - doTail; + doEofCheck; end if; -- Always the same outbound AXIS stream width From 854aa0b04967357f5dbff13112e2c5e4e0dd174a Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Wed, 20 Sep 2023 14:55:51 -0700 Subject: [PATCH 26/45] Update Pgp4TxLiteWrapper.vhd ### Description - Cadence Genus will give an error if the port has a default value on the entity definition but not connected at the component instantiation. - This PR resolves this error --- protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd index 780e19d25b..a7dee767d5 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd @@ -83,6 +83,11 @@ begin pgpTxActive => '1', pgpTxMasters(0) => pgpTxMaster, pgpTxSlaves(0) => pgpTxSlave, + -- Status of receive and remote FIFOs (Asynchronous) + locRxFifoCtrl(0)=> AXI_STREAM_CTRL_UNUSED_C, + locRxLinkReady => '1', + remRxFifoCtrl(0)=> AXI_STREAM_CTRL_UNUSED_C, + remRxLinkReady => '1', -- PHY interface phyTxActive => '1', phyTxReady => phyTxReady, From ee47639c5832a030b3e01ac5221a0ff4b2cb7afd Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 22 Sep 2023 13:49:41 -0700 Subject: [PATCH 27/45] .sh whitespace removal --- ghdl-build.sh | 2 +- scripts/generateDocumentationAndDeploy.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/ghdl-build.sh b/ghdl-build.sh index 3915889e6e..035036d0c4 100755 --- a/ghdl-build.sh +++ b/ghdl-build.sh @@ -9,7 +9,7 @@ # the terms contained in the LICENSE.txt file. #----------------------------------------------------------------------------- -# Note: The manually installing of ghdl v3.0.0 until supported in Github Action's Ubuntu LTS +# Note: The manually installing of ghdl v3.0.0 until supported in Github Action's Ubuntu LTS echo 'Installing GHDL ...' sudo apt update diff --git a/scripts/generateDocumentationAndDeploy.sh b/scripts/generateDocumentationAndDeploy.sh index db81602698..7a2698fde8 100644 --- a/scripts/generateDocumentationAndDeploy.sh +++ b/scripts/generateDocumentationAndDeploy.sh @@ -88,7 +88,7 @@ echo "" > .nojekyll echo 'Generating Doxygen code documentation...' doxygen -v -# Update the INPUT configuration +# Update the INPUT configuration echo "INPUT = $TRAVIS_BUILD_DIR" >> $DOXYFILE # Update the EXCLUDE configuration From d8199967b8de2979012d691d38ff32e7fe3f2844 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 22 Sep 2023 13:50:30 -0700 Subject: [PATCH 28/45] .vh whitespace removal --- .../Micron/ddr3/tb/1024Mb_ddr3_parameters.vh | 58 +++++++++---------- .../Micron/ddr3/tb/2048Mb_ddr3_parameters.vh | 58 +++++++++---------- .../Micron/ddr3/tb/4096Mb_ddr3_parameters.vh | 58 +++++++++---------- .../Micron/ddr3/tb/8192Mb_ddr3_parameters.vh | 50 ++++++++-------- 4 files changed, 112 insertions(+), 112 deletions(-) diff --git a/devices/Micron/ddr3/tb/1024Mb_ddr3_parameters.vh b/devices/Micron/ddr3/tb/1024Mb_ddr3_parameters.vh index d42ba3fc94..934a37cdd8 100644 --- a/devices/Micron/ddr3/tb/1024Mb_ddr3_parameters.vh +++ b/devices/Micron/ddr3/tb/1024Mb_ddr3_parameters.vh @@ -1,24 +1,24 @@ /**************************************************************************************** * -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the +* Disclaimer This software code and all associated documentation, comments or other +* of Warranty: information (collectively "Software") is provided "AS IS" without +* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY +* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES +* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT +* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE +* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. +* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR +* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE +* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, +* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, +* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, +* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, +* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE +* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +* DAMAGES. Because some jurisdictions prohibit the exclusion or +* limitation of liability for consequential or incidental damages, the * above limitation may not apply to you. * * Copyright 2003 Micron Technology, Inc. All rights reserved. @@ -54,7 +54,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width parameter TIS = 35; // tIS ps Input Setup Time parameter TIH = 75; // tIH ps Input Hold Time parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time @@ -94,7 +94,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width parameter TIS = 50; // tIS ps Input Setup Time parameter TIH = 100; // tIH ps Input Hold Time parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time @@ -134,7 +134,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width parameter TIS = 170; // tIS ps Input Setup Time parameter TIH = 120; // tIH ps Input Hold Time parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time @@ -174,7 +174,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width parameter TIS = 190; // tIS ps Input Setup Time parameter TIH = 140; // tIH ps Input Hold Time parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time @@ -214,7 +214,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width parameter TIS = 190; // tIS ps Input Setup Time parameter TIH = 140; // tIH ps Input Hold Time parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time @@ -254,7 +254,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width parameter TIS = 275; // tIS ps Input Setup Time parameter TIH = 200; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -294,7 +294,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width parameter TIS = 275; // tIS ps Input Setup Time parameter TIH = 200; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -334,7 +334,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width parameter TIS = 350; // tIS ps Input Setup Time parameter TIH = 275; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -375,7 +375,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width parameter TIS = 350; // tIS ps Input Setup Time parameter TIH = 275; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -478,7 +478,7 @@ parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - + // Data OUT parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# // Data Strobe OUT diff --git a/devices/Micron/ddr3/tb/2048Mb_ddr3_parameters.vh b/devices/Micron/ddr3/tb/2048Mb_ddr3_parameters.vh index 6fcfffb5d7..eaaa813ab8 100644 --- a/devices/Micron/ddr3/tb/2048Mb_ddr3_parameters.vh +++ b/devices/Micron/ddr3/tb/2048Mb_ddr3_parameters.vh @@ -1,24 +1,24 @@ /**************************************************************************************** * -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the +* Disclaimer This software code and all associated documentation, comments or other +* of Warranty: information (collectively "Software") is provided "AS IS" without +* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY +* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES +* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT +* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE +* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. +* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR +* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE +* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, +* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, +* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, +* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, +* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE +* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +* DAMAGES. Because some jurisdictions prohibit the exclusion or +* limitation of liability for consequential or incidental damages, the * above limitation may not apply to you. * * Copyright 2003 Micron Technology, Inc. All rights reserved. @@ -54,7 +54,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width parameter TIS = 35; // tIS ps Input Setup Time parameter TIH = 75; // tIH ps Input Hold Time parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time @@ -94,7 +94,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width parameter TIS = 50; // tIS ps Input Setup Time parameter TIH = 100; // tIH ps Input Hold Time parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time @@ -134,7 +134,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width parameter TIS = 170; // tIS ps Input Setup Time parameter TIH = 120; // tIH ps Input Hold Time parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time @@ -174,7 +174,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width parameter TIS = 190; // tIS ps Input Setup Time parameter TIH = 140; // tIH ps Input Hold Time parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time @@ -214,7 +214,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width parameter TIS = 190; // tIS ps Input Setup Time parameter TIH = 140; // tIH ps Input Hold Time parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time @@ -254,7 +254,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width parameter TIS = 275; // tIS ps Input Setup Time parameter TIH = 200; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -294,7 +294,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width parameter TIS = 275; // tIS ps Input Setup Time parameter TIH = 200; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -334,7 +334,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width parameter TIS = 350; // tIS ps Input Setup Time parameter TIH = 275; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -375,7 +375,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width parameter TIS = 350; // tIS ps Input Setup Time parameter TIH = 275; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -466,7 +466,7 @@ parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - + // Data OUT parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# // Data Strobe OUT diff --git a/devices/Micron/ddr3/tb/4096Mb_ddr3_parameters.vh b/devices/Micron/ddr3/tb/4096Mb_ddr3_parameters.vh index e9e7e93136..a5fe950670 100644 --- a/devices/Micron/ddr3/tb/4096Mb_ddr3_parameters.vh +++ b/devices/Micron/ddr3/tb/4096Mb_ddr3_parameters.vh @@ -1,24 +1,24 @@ /**************************************************************************************** * -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the +* Disclaimer This software code and all associated documentation, comments or other +* of Warranty: information (collectively "Software") is provided "AS IS" without +* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY +* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES +* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT +* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE +* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. +* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR +* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE +* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, +* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, +* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, +* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, +* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE +* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +* DAMAGES. Because some jurisdictions prohibit the exclusion or +* limitation of liability for consequential or incidental damages, the * above limitation may not apply to you. * * Copyright 2003 Micron Technology, Inc. All rights reserved. @@ -54,7 +54,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width parameter TIS = 35; // tIS ps Input Setup Time parameter TIH = 75; // tIH ps Input Hold Time parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time @@ -94,7 +94,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width parameter TIS = 50; // tIS ps Input Setup Time parameter TIH = 100; // tIH ps Input Hold Time parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time @@ -134,7 +134,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width parameter TIS = 170; // tIS ps Input Setup Time parameter TIH = 120; // tIH ps Input Hold Time parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time @@ -174,7 +174,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width parameter TIS = 190; // tIS ps Input Setup Time parameter TIH = 140; // tIH ps Input Hold Time parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time @@ -214,7 +214,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width parameter TIS = 190; // tIS ps Input Setup Time parameter TIH = 140; // tIH ps Input Hold Time parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time @@ -254,7 +254,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width parameter TIS = 275; // tIS ps Input Setup Time parameter TIH = 200; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -294,7 +294,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width parameter TIS = 275; // tIS ps Input Setup Time parameter TIH = 200; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -334,7 +334,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width parameter TIS = 350; // tIS ps Input Setup Time parameter TIH = 275; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -375,7 +375,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width parameter TIS = 350; // tIS ps Input Setup Time parameter TIH = 275; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -466,7 +466,7 @@ parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - + // Data OUT parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# // Data Strobe OUT diff --git a/devices/Micron/ddr3/tb/8192Mb_ddr3_parameters.vh b/devices/Micron/ddr3/tb/8192Mb_ddr3_parameters.vh index c6848ad0d2..9a99186149 100644 --- a/devices/Micron/ddr3/tb/8192Mb_ddr3_parameters.vh +++ b/devices/Micron/ddr3/tb/8192Mb_ddr3_parameters.vh @@ -1,24 +1,24 @@ /**************************************************************************************** * -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the +* Disclaimer This software code and all associated documentation, comments or other +* of Warranty: information (collectively "Software") is provided "AS IS" without +* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY +* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES +* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT +* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE +* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. +* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR +* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE +* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, +* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, +* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, +* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, +* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE +* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +* DAMAGES. Because some jurisdictions prohibit the exclusion or +* limitation of liability for consequential or incidental damages, the * above limitation may not apply to you. * * Copyright 2003 Micron Technology, Inc. All rights reserved. @@ -54,7 +54,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width parameter TIS = 35; // tIS ps Input Setup Time parameter TIH = 75; // tIH ps Input Hold Time parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time @@ -94,7 +94,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width parameter TIS = 50; // tIS ps Input Setup Time parameter TIH = 100; // tIH ps Input Hold Time parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time @@ -134,7 +134,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width parameter TIS = 170; // tIS ps Input Setup Time parameter TIH = 120; // tIH ps Input Hold Time parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time @@ -174,7 +174,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width parameter TIS = 190; // tIS ps Input Setup Time parameter TIH = 140; // tIH ps Input Hold Time parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time @@ -215,7 +215,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width parameter TIS = 275; // tIS ps Input Setup Time parameter TIH = 200; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -306,7 +306,7 @@ parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - + // Data OUT parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# // Data Strobe OUT From 24dd43cab0168b4158f8554164cf9500f9d5fa4d Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 22 Sep 2023 13:52:22 -0700 Subject: [PATCH 29/45] .c/.h whitespace removal --- axi/simlink/src/RogueSideBand.c | 24 +- axi/simlink/src/RogueSideBand.h | 18 +- axi/simlink/src/RogueTcpMemory.c | 36 +- axi/simlink/src/RogueTcpMemory.h | 18 +- axi/simlink/src/RogueTcpStream.c | 32 +- axi/simlink/src/RogueTcpStream.h | 14 +- axi/simlink/src/VhpiGeneric.c | 30 +- axi/simlink/src/VhpiGeneric.h | 16 +- base/general/simlink/src/VhpiGeneric.c | 24 +- base/general/simlink/src/VhpiGeneric.h | 16 +- protocols/jtag/xvcSrv/src/mmioHelper.h | 12 +- protocols/jtag/xvcSrv/src/xvcConn.h | 12 +- protocols/jtag/xvcSrv/src/xvcDriver.h | 12 +- protocols/jtag/xvcSrv/src/xvcDrvAxisFifo.h | 12 +- protocols/jtag/xvcSrv/src/xvcDrvLoopBack.h | 12 +- protocols/jtag/xvcSrv/src/xvcDrvUdp.h | 12 +- protocols/jtag/xvcSrv/src/xvcSrv.h | 12 +- xilinx/general/sdk/common/printf.c | 490 ++++++++++----------- xilinx/general/sdk/common/printf.h | 248 +++++------ xilinx/general/sdk/common/ssi_printf.c | 18 +- xilinx/general/sdk/common/ssi_printf.h | 10 +- 21 files changed, 539 insertions(+), 539 deletions(-) diff --git a/axi/simlink/src/RogueSideBand.c b/axi/simlink/src/RogueSideBand.c index b1bc374661..43e6b54e34 100755 --- a/axi/simlink/src/RogueSideBand.c +++ b/axi/simlink/src/RogueSideBand.c @@ -1,10 +1,10 @@ ////////////////////////////////////////////////////////////////////////////// // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. ////////////////////////////////////////////////////////////////////////////// @@ -27,17 +27,17 @@ void RogueSideBandRestart(RogueSideBandData *data, portDataT *portData) { char buffer[100]; - if ( data->zmqPush != NULL ) zmq_close(data->zmqPush ); + if ( data->zmqPush != NULL ) zmq_close(data->zmqPush ); if ( data->zmqPull != NULL ) zmq_close(data->zmqPull); if ( data->zmqCtx != NULL ) zmq_term(data->zmqCtx); data->zmqCtx = NULL; data->zmqPush = NULL; data->zmqPull = NULL; - + data->zmqCtx = zmq_ctx_new(); data->zmqPull = zmq_socket(data->zmqCtx,ZMQ_PULL); - data->zmqPush = zmq_socket(data->zmqCtx,ZMQ_PUSH); + data->zmqPush = zmq_socket(data->zmqCtx,ZMQ_PUSH); vhpi_printf("RogueSideBand: Listening on ports %i & %i\n",data->port, data->port+1); @@ -52,7 +52,7 @@ void RogueSideBandRestart(RogueSideBandData *data, portDataT *portData) { vhpi_assert("RogueSideBand: Failed to bind push port",vhpiFatal); return; } - + } // Send a message @@ -61,7 +61,7 @@ void RogueSideBandSend ( RogueSideBandData *data, portDataT *portData ) { uint8_t ba[4]; char buffer[200]; - if ( (zmq_msg_init_size(&msg,4) < 0) ) { + if ( (zmq_msg_init_size(&msg,4) < 0) ) { vhpi_assert("RogueSideBand: Failed to init message",vhpiFatal); return; } @@ -119,7 +119,7 @@ int RogueSideBandRecv ( RogueSideBandData *data, portDataT *portData ) { } // Init function -void RogueSideBandInit(vhpiHandleT compInst) { +void RogueSideBandInit(vhpiHandleT compInst) { // Create new port data structure portDataT *portData = (portDataT *) malloc(sizeof(portDataT)); @@ -188,7 +188,7 @@ void RogueSideBandUpdate ( void *userPtr ) { data->rxOpCode = 0x00; data->rxOpCodeEn = 0; data->txRemData = 0x00; - data->txRemDataChanged = 0x00; + data->txRemDataChanged = 0x00; data->txOpCode = 0x00; data->txOpCodeEn = 0; setInt(s_rxOpCodeEn,0); diff --git a/axi/simlink/src/RogueSideBand.h b/axi/simlink/src/RogueSideBand.h index 1df1779393..c82bf01ea1 100755 --- a/axi/simlink/src/RogueSideBand.h +++ b/axi/simlink/src/RogueSideBand.h @@ -1,10 +1,10 @@ ////////////////////////////////////////////////////////////////////////////// // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. ////////////////////////////////////////////////////////////////////////////// @@ -35,20 +35,20 @@ typedef struct { uint32_t currClk; uint16_t port; - + uint8_t rxRemData; uint8_t rxOpCode; uint8_t rxOpCodeEn; uint8_t txRemData; - uint8_t txRemDataChanged; + uint8_t txRemDataChanged; uint8_t txOpCode; uint8_t txOpCodeEn; void * zmqCtx; void * zmqPull; - void * zmqPush; - + void * zmqPush; + } RogueSideBandData; // Init function diff --git a/axi/simlink/src/RogueTcpMemory.c b/axi/simlink/src/RogueTcpMemory.c index 53d4b3fa68..a08fc0e3da 100755 --- a/axi/simlink/src/RogueTcpMemory.c +++ b/axi/simlink/src/RogueTcpMemory.c @@ -1,10 +1,10 @@ ////////////////////////////////////////////////////////////////////////////// // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. ////////////////////////////////////////////////////////////////////////////// @@ -34,7 +34,7 @@ void RogueTcpMemoryRestart(RogueTcpMemoryData *data, portDataT *portData) { data->zmqCtx = NULL; data->zmqPull = NULL; data->zmqPush = NULL; - + data->zmqCtx = zmq_ctx_new(); data->zmqPull = zmq_socket(data->zmqCtx,ZMQ_PULL); data->zmqPush = zmq_socket(data->zmqCtx,ZMQ_PUSH); @@ -61,9 +61,9 @@ void RogueTcpMemorySend ( RogueTcpMemoryData *data, portDataT *portData ) { zmq_msg_t msg[6]; if ( (zmq_msg_init_size(&(msg[0]),4) < 0) || // ID - (zmq_msg_init_size(&(msg[1]),8) < 0) || // Addr - (zmq_msg_init_size(&(msg[2]),4) < 0) || // Size - (zmq_msg_init_size(&(msg[3]),4) < 0) || // type + (zmq_msg_init_size(&(msg[1]),8) < 0) || // Addr + (zmq_msg_init_size(&(msg[2]),4) < 0) || // Size + (zmq_msg_init_size(&(msg[3]),4) < 0) || // type (zmq_msg_init_size(&(msg[5]),4) < 0) ) { // result vhpi_assert("RogueTcpMemory: Failed to init message header",vhpiFatal); return; @@ -82,7 +82,7 @@ void RogueTcpMemorySend ( RogueTcpMemoryData *data, portDataT *portData ) { // Copy data memcpy(zmq_msg_data(&(msg[4])),data->data,data->size); - + // Send data for (x=0; x < 6; x++) { if ( zmq_sendmsg(data->zmqPush,&(msg[x]),(x==5)?0:ZMQ_SNDMORE) < 0 ) @@ -162,7 +162,7 @@ int RogueTcpMemoryRecv ( RogueTcpMemoryData *data, portDataT *portData ) { } // Init function -void RogueTcpMemoryInit(vhpiHandleT compInst) { +void RogueTcpMemoryInit(vhpiHandleT compInst) { // Create new port data structure portDataT *portData = (portDataT *) malloc(sizeof(portDataT)); @@ -172,9 +172,9 @@ void RogueTcpMemoryInit(vhpiHandleT compInst) { portData->portCount = PORT_COUNT; // Set port directions - portData->portDir[s_clock] = vhpiIn; - portData->portDir[s_reset] = vhpiIn; - portData->portDir[s_port] = vhpiIn; + portData->portDir[s_clock] = vhpiIn; + portData->portDir[s_reset] = vhpiIn; + portData->portDir[s_port] = vhpiIn; portData->portDir[s_araddr] = vhpiOut; portData->portDir[s_arprot] = vhpiOut; @@ -200,9 +200,9 @@ void RogueTcpMemoryInit(vhpiHandleT compInst) { portData->portDir[s_bvalid] = vhpiIn; // Set port widths - portData->portWidth[s_clock] = 1; - portData->portWidth[s_reset] = 1; - portData->portWidth[s_port] = 16; + portData->portWidth[s_clock] = 1; + portData->portWidth[s_reset] = 1; + portData->portWidth[s_port] = 16; portData->portWidth[s_araddr] = 32; portData->portWidth[s_arprot] = 3; @@ -262,7 +262,7 @@ void RogueTcpMemoryUpdate ( void *userPtr ) { setInt(s_rready,1); setInt(s_awvalid,0); setInt(s_bready,1); - } + } // Data movement else { diff --git a/axi/simlink/src/RogueTcpMemory.h b/axi/simlink/src/RogueTcpMemory.h index 97bafa48a0..a081fdb03d 100755 --- a/axi/simlink/src/RogueTcpMemory.h +++ b/axi/simlink/src/RogueTcpMemory.h @@ -1,10 +1,10 @@ ////////////////////////////////////////////////////////////////////////////// // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. ////////////////////////////////////////////////////////////////////////////// @@ -66,12 +66,12 @@ typedef struct { uint8_t arprot; uint8_t arvalid; uint8_t rready; - + uint8_t arready; uint32_t rdata; uint8_t rresp; uint8_t rvalid; - + uint32_t awaddr; uint8_t awprot; uint8_t awvalid; @@ -79,7 +79,7 @@ typedef struct { uint8_t wstrb; uint8_t wvalid; uint8_t bready; - + uint8_t awready; uint8_t wready; uint8_t bresp; @@ -100,7 +100,7 @@ typedef struct { void * zmqCtx; void * zmqPull; void * zmqPush; - + } RogueTcpMemoryData; // Init function diff --git a/axi/simlink/src/RogueTcpStream.c b/axi/simlink/src/RogueTcpStream.c index c67dd1db77..e7f77a0faf 100755 --- a/axi/simlink/src/RogueTcpStream.c +++ b/axi/simlink/src/RogueTcpStream.c @@ -1,10 +1,10 @@ ////////////////////////////////////////////////////////////////////////////// // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. ////////////////////////////////////////////////////////////////////////////// @@ -35,7 +35,7 @@ void RogueTcpStreamRestart(RogueTcpStreamData *data, portDataT *portData) { data->zmqCtx = NULL; data->zmqPush = NULL; data->zmqPull = NULL; - + data->zmqCtx = zmq_ctx_new(); data->zmqPull = zmq_socket(data->zmqCtx,ZMQ_PULL); data->zmqPush = zmq_socket(data->zmqCtx,ZMQ_PUSH); @@ -93,7 +93,7 @@ void RogueTcpStreamSend ( RogueTcpStreamData *data, portDataT *portData ) { // Copy data memcpy(zmq_msg_data(&(msg[3])),data->ibData,data->ibSize); - + // Send data for (x=0; x < 4; x++) { if ( zmq_msg_send(&(msg[x]), data->zmqPush, (x==3)?0:ZMQ_SNDMORE) < 0 ) { @@ -180,7 +180,7 @@ int RogueTcpStreamRecv ( RogueTcpStreamData *data, portDataT *portData ) { // Init function -void RogueTcpStreamInit(vhpiHandleT compInst) { +void RogueTcpStreamInit(vhpiHandleT compInst) { // Create new port data structure portDataT *portData = (portDataT *) malloc(sizeof(portDataT)); @@ -190,10 +190,10 @@ void RogueTcpStreamInit(vhpiHandleT compInst) { portData->portCount = PORT_COUNT; // Set port directions - portData->portDir[s_clock] = vhpiIn; - portData->portDir[s_reset] = vhpiIn; - portData->portDir[s_port] = vhpiIn; - portData->portDir[s_ssi] = vhpiIn; + portData->portDir[s_clock] = vhpiIn; + portData->portDir[s_reset] = vhpiIn; + portData->portDir[s_port] = vhpiIn; + portData->portDir[s_ssi] = vhpiIn; portData->portDir[s_obValid] = vhpiOut; portData->portDir[s_obReady] = vhpiIn; @@ -204,7 +204,7 @@ void RogueTcpStreamInit(vhpiHandleT compInst) { portData->portDir[s_obKeep] = vhpiOut; portData->portDir[s_obLast] = vhpiOut; - portData->portDir[s_ibValid] = vhpiIn; + portData->portDir[s_ibValid] = vhpiIn; portData->portDir[s_ibReady] = vhpiOut; portData->portDir[s_ibDataLow] = vhpiIn; portData->portDir[s_ibDataHigh] = vhpiIn; @@ -285,7 +285,7 @@ void RogueTcpStreamUpdate ( void *userPtr ) { setInt(s_obUserHigh,0); setInt(s_obKeep,0); setInt(s_obLast,0); - } + } // Data movement else { @@ -341,7 +341,7 @@ void RogueTcpStreamUpdate ( void *userPtr ) { if ( data->obCount == 0 ) setInt(s_obUserLow,data->obFuser); else setInt(s_obUserLow,0); setInt(s_obUserHigh,0); - + // Get data dHigh = 0; dLow = 0; @@ -362,7 +362,7 @@ void RogueTcpStreamUpdate ( void *userPtr ) { } else { dHigh |= (data->obData[data->obCount] << ((x-4)*8)); - if ( (data->obCount+1) == data->obSize ) + if ( (data->obCount+1) == data->obSize ) setInt(s_obUserHigh,(data->obLuser << ((x-4)*8))); } diff --git a/axi/simlink/src/RogueTcpStream.h b/axi/simlink/src/RogueTcpStream.h index 95382d650c..e4091ad73e 100755 --- a/axi/simlink/src/RogueTcpStream.h +++ b/axi/simlink/src/RogueTcpStream.h @@ -1,10 +1,10 @@ ////////////////////////////////////////////////////////////////////////////// // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. ////////////////////////////////////////////////////////////////////////////// @@ -62,11 +62,11 @@ typedef struct { uint16_t port; uint8_t ssi; time_t ltime; - + void * zmqCtx; void * zmqPush; void * zmqPull; - + } RogueTcpStreamData; // Init function diff --git a/axi/simlink/src/VhpiGeneric.c b/axi/simlink/src/VhpiGeneric.c index 89e89f7e92..22d6984323 100755 --- a/axi/simlink/src/VhpiGeneric.c +++ b/axi/simlink/src/VhpiGeneric.c @@ -12,11 +12,11 @@ // and only has to set the width and the in/out types for each port. //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- // Modification history: @@ -48,7 +48,7 @@ void VhpiGenericConvertIn( portDataT *portData ) { for (x=0; x < portData->portCount; x++) { if ( portData->portDir[x] != vhpiOut ) { if ( portData->portWidth[x] == 1 ) { - if ( portData->portValue[x]->value.enumval == 3 ) + if ( portData->portValue[x]->value.enumval == 3 ) portData->intValue[x] = 1; else portData->intValue[x] = 0; @@ -57,7 +57,7 @@ void VhpiGenericConvertIn( portDataT *portData ) { portData->intValue[x] = 0; for (y=0; y < portData->portWidth[x]; y++) { bit = (portData->portWidth[x] - 1) - y; - if ( portData->portValue[x]->value.enums[y] == 3 ) + if ( portData->portValue[x]->value.enums[y] == 3 ) portData->intValue[x] += 1<portValue[x]->value.enums[y] = 2; } } - else + else for (y=0; y < portData->portWidth[x]; y++) { portData->portValue[x]->value.enums[y] = 4; // Tri-state } @@ -136,7 +136,7 @@ void VhpiGenericCallBack(vhpiCbDataT *cbData ) { // Set output values for (x=0; x < portData->portCount; x++) { - if ( portData->portDir[x] != vhpiIn ) + if ( portData->portDir[x] != vhpiIn ) if ( (ret = vhpi_put_value(portData->portHandle[x],portData->portValue[x], vhpiForcePropagate))) vhpi_printf("vhpi_put_value status error %i for port %i\n",ret,x); } @@ -152,7 +152,7 @@ void VhpiGenericErrors ( vhpiCbDataT *cb ) { // Function that is called as the module is elaborated. -// Here we will simply register an error handling callback function. +// Here we will simply register an error handling callback function. void VhpiGenericElab(vhpiHandleT compInst) { // Create callback structure, setup callback function @@ -160,16 +160,16 @@ void VhpiGenericElab(vhpiHandleT compInst) { pCbData->cbf = VhpiGenericErrors; pCbData->time = (vhpiTimeT*) malloc(sizeof(vhpiTimeT)); pCbData->reason = vhpiCbPLIError; - + #if (VCS_VERSION >= 2016) vhpi_register_cb(pCbData,vhpiReturnCb); #else vhpi_register_cb(pCbData); -#endif +#endif } -// Function that is called as the module is initialized. +// Function that is called as the module is initialized. // Check ports and setup functions to handle clock changes void VhpiGenericInit(vhpiHandleT compInst, portDataT *portData ) { @@ -208,7 +208,7 @@ void VhpiGenericInit(vhpiHandleT compInst, portDataT *portData ) { width = vhpi_value_size(portData->portHandle[x],vhpiEnumVecVal); portData->portValue[x]->value.enums = (vhpiEnumT*)malloc(width); portData->portValue[x]->bufSize = width; - for (y=0; y < portData->portWidth[x]; y++ ) + for (y=0; y < portData->portWidth[x]; y++ ) portData->portValue[x]->value.enums[y] = 2; } @@ -244,6 +244,6 @@ void VhpiGenericInit(vhpiHandleT compInst, portDataT *portData ) { vhpi_register_cb(cbData,vhpiReturnCb); #else vhpi_register_cb(cbData); - #endif + #endif } } diff --git a/axi/simlink/src/VhpiGeneric.h b/axi/simlink/src/VhpiGeneric.h index 8921bb44cb..0d18c2946d 100755 --- a/axi/simlink/src/VhpiGeneric.h +++ b/axi/simlink/src/VhpiGeneric.h @@ -8,14 +8,14 @@ //----------------------------------------------------------------------------- // Description: // This is a generic block of code to handle the low level interface to the -// VHDL simulator. +// VHDL simulator. //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- // Modification history: @@ -59,7 +59,7 @@ typedef struct portDataS { // Current simulation time vhpiTimeT simTime; - + // Name of block char *blockName; @@ -72,7 +72,7 @@ typedef struct portDataS { } portDataT; -// Function that is called as the module is initialized. +// Function that is called as the module is initialized. // Check ports and setup functions to handle clock changes void VhpiGenericInit(vhpiHandleT compInst, portDataT *portData ); diff --git a/base/general/simlink/src/VhpiGeneric.c b/base/general/simlink/src/VhpiGeneric.c index 8891a5798c..769cd3430f 100755 --- a/base/general/simlink/src/VhpiGeneric.c +++ b/base/general/simlink/src/VhpiGeneric.c @@ -12,11 +12,11 @@ // and only has to set the width and the in/out types for each port. //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- // Modification history: @@ -49,7 +49,7 @@ void VhpiGenericConvertIn( portDataT *portData ) { for (x=0; x < portData->portCount; x++) { if ( portData->portDir[x] != vhpiOut ) { if ( portData->portWidth[x] == 1 ) { - if ( portData->portValue[x]->value.enumval == 3 ) + if ( portData->portValue[x]->value.enumval == 3 ) portData->intValue[x] = 1; else portData->intValue[x] = 0; @@ -58,7 +58,7 @@ void VhpiGenericConvertIn( portDataT *portData ) { portData->intValue[x] = 0; for (y=0; y < portData->portWidth[x]; y++) { bit = (portData->portWidth[x] - 1) - y; - if ( portData->portValue[x]->value.enums[y] == 3 ) + if ( portData->portValue[x]->value.enums[y] == 3 ) portData->intValue[x] += 1<portValue[x]->value.enums[y] = 2; } } - else + else for (y=0; y < portData->portWidth[x]; y++) { portData->portValue[x]->value.enums[y] = 4; // Tri-state } @@ -135,7 +135,7 @@ void VhpiGenericCallBack(vhpiCbDataT *cbData ) { // Set output values for (x=0; x < portData->portCount; x++) { - if ( portData->portDir[x] != vhpiIn ) + if ( portData->portDir[x] != vhpiIn ) vhpi_put_value(portData->portHandle[x],portData->portValue[x], vhpiForcePropagate); } } @@ -150,7 +150,7 @@ void VhpiGenericErrors ( vhpiCbDataT *cb ) { // Function that is called as the module is elaborated. -// Here we will simply register an error handling callback function. +// Here we will simply register an error handling callback function. void VhpiGenericElab(vhpiHandleT compInst) { // Create callback structure, setup callback function @@ -162,7 +162,7 @@ void VhpiGenericElab(vhpiHandleT compInst) { } -// Function that is called as the module is initialized. +// Function that is called as the module is initialized. // Check ports and setup functions to handle clock changes void VhpiGenericInit(vhpiHandleT compInst, portDataT *portData ) { @@ -198,7 +198,7 @@ void VhpiGenericInit(vhpiHandleT compInst, portDataT *portData ) { portData->portValue[x]->format = vhpiEnumVecVal; width = vhpi_value_size(portData->portHandle[x],vhpiEnumVecVal); portData->portValue[x]->value.enums = (vhpiEnumT*)malloc(width); - for (y=0; y < portData->portWidth[x]; y++ ) + for (y=0; y < portData->portWidth[x]; y++ ) portData->portValue[x]->value.enums[y] = 2; } diff --git a/base/general/simlink/src/VhpiGeneric.h b/base/general/simlink/src/VhpiGeneric.h index 8921bb44cb..0d18c2946d 100755 --- a/base/general/simlink/src/VhpiGeneric.h +++ b/base/general/simlink/src/VhpiGeneric.h @@ -8,14 +8,14 @@ //----------------------------------------------------------------------------- // Description: // This is a generic block of code to handle the low level interface to the -// VHDL simulator. +// VHDL simulator. //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- // Modification history: @@ -59,7 +59,7 @@ typedef struct portDataS { // Current simulation time vhpiTimeT simTime; - + // Name of block char *blockName; @@ -72,7 +72,7 @@ typedef struct portDataS { } portDataT; -// Function that is called as the module is initialized. +// Function that is called as the module is initialized. // Check ports and setup functions to handle clock changes void VhpiGenericInit(vhpiHandleT compInst, portDataT *portData ); diff --git a/protocols/jtag/xvcSrv/src/mmioHelper.h b/protocols/jtag/xvcSrv/src/mmioHelper.h index ff72ecac2c..9a82723002 100644 --- a/protocols/jtag/xvcSrv/src/mmioHelper.h +++ b/protocols/jtag/xvcSrv/src/mmioHelper.h @@ -3,14 +3,14 @@ //----------------------------------------------------------------------------- // Company : SLAC National Accelerator Laboratory //----------------------------------------------------------------------------- -// Description: +// Description: //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- diff --git a/protocols/jtag/xvcSrv/src/xvcConn.h b/protocols/jtag/xvcSrv/src/xvcConn.h index 18c937fc24..da38543b15 100644 --- a/protocols/jtag/xvcSrv/src/xvcConn.h +++ b/protocols/jtag/xvcSrv/src/xvcConn.h @@ -3,14 +3,14 @@ //----------------------------------------------------------------------------- // Company : SLAC National Accelerator Laboratory //----------------------------------------------------------------------------- -// Description: +// Description: //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- diff --git a/protocols/jtag/xvcSrv/src/xvcDriver.h b/protocols/jtag/xvcSrv/src/xvcDriver.h index aeadbc9374..8951be3b10 100644 --- a/protocols/jtag/xvcSrv/src/xvcDriver.h +++ b/protocols/jtag/xvcSrv/src/xvcDriver.h @@ -3,14 +3,14 @@ //----------------------------------------------------------------------------- // Company : SLAC National Accelerator Laboratory //----------------------------------------------------------------------------- -// Description: +// Description: //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- diff --git a/protocols/jtag/xvcSrv/src/xvcDrvAxisFifo.h b/protocols/jtag/xvcSrv/src/xvcDrvAxisFifo.h index e394bf9e65..d1d9bdf7fb 100644 --- a/protocols/jtag/xvcSrv/src/xvcDrvAxisFifo.h +++ b/protocols/jtag/xvcSrv/src/xvcDrvAxisFifo.h @@ -3,14 +3,14 @@ //----------------------------------------------------------------------------- // Company : SLAC National Accelerator Laboratory //----------------------------------------------------------------------------- -// Description: +// Description: //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- diff --git a/protocols/jtag/xvcSrv/src/xvcDrvLoopBack.h b/protocols/jtag/xvcSrv/src/xvcDrvLoopBack.h index d841a04419..277e6a6c88 100644 --- a/protocols/jtag/xvcSrv/src/xvcDrvLoopBack.h +++ b/protocols/jtag/xvcSrv/src/xvcDrvLoopBack.h @@ -3,14 +3,14 @@ //----------------------------------------------------------------------------- // Company : SLAC National Accelerator Laboratory //----------------------------------------------------------------------------- -// Description: +// Description: //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- diff --git a/protocols/jtag/xvcSrv/src/xvcDrvUdp.h b/protocols/jtag/xvcSrv/src/xvcDrvUdp.h index d1649542e9..d0dc69e699 100644 --- a/protocols/jtag/xvcSrv/src/xvcDrvUdp.h +++ b/protocols/jtag/xvcSrv/src/xvcDrvUdp.h @@ -3,14 +3,14 @@ //----------------------------------------------------------------------------- // Company : SLAC National Accelerator Laboratory //----------------------------------------------------------------------------- -// Description: +// Description: //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- diff --git a/protocols/jtag/xvcSrv/src/xvcSrv.h b/protocols/jtag/xvcSrv/src/xvcSrv.h index 28a357e38a..a361b91d77 100644 --- a/protocols/jtag/xvcSrv/src/xvcSrv.h +++ b/protocols/jtag/xvcSrv/src/xvcSrv.h @@ -3,14 +3,14 @@ //----------------------------------------------------------------------------- // Company : SLAC National Accelerator Laboratory //----------------------------------------------------------------------------- -// Description: +// Description: //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- diff --git a/xilinx/general/sdk/common/printf.c b/xilinx/general/sdk/common/printf.c index ebcb5f3b7e..5c3d85679b 100755 --- a/xilinx/general/sdk/common/printf.c +++ b/xilinx/general/sdk/common/printf.c @@ -1,245 +1,245 @@ -/* - * Copyright (c) 2004,2012 Kustaa Nyholm / SpareTimeLabs - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * Neither the name of the Kustaa Nyholm or SpareTimeLabs nor the names of its - * contributors may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - */ - -#include "printf.h" - -typedef void (*putcf) (void*,char); -static putcf stdout_putf; -static void* stdout_putp; - - -#ifdef PRINTF_LONG_SUPPORT - -static void uli2a(unsigned long int num, unsigned int base, int uc,char * bf) - { - int n=0; - unsigned int d=1; - while (num/d >= base) - d*=base; - while (d!=0) { - int dgt = num / d; - num%=d; - d/=base; - if (n || dgt>0|| d==0) { - *bf++ = dgt+(dgt<10 ? '0' : (uc ? 'A' : 'a')-10); - ++n; - } - } - *bf=0; - } - -static void li2a (long num, char * bf) - { - if (num<0) { - num=-num; - *bf++ = '-'; - } - uli2a(num,10,0,bf); - } - -#endif - -static void ui2a(unsigned int num, unsigned int base, int uc,char * bf) - { - int n=0; - unsigned int d=1; - while (num/d >= base) - d*=base; - while (d!=0) { - int dgt = num / d; - num%= d; - d/=base; - if (n || dgt>0 || d==0) { - *bf++ = dgt+(dgt<10 ? '0' : (uc ? 'A' : 'a')-10); - ++n; - } - } - *bf=0; - } - -static void i2a (int num, char * bf) - { - if (num<0) { - num=-num; - *bf++ = '-'; - } - ui2a(num,10,0,bf); - } - -static int a2d(char ch) - { - if (ch>='0' && ch<='9') - return ch-'0'; - else if (ch>='a' && ch<='f') - return ch-'a'+10; - else if (ch>='A' && ch<='F') - return ch-'A'+10; - else return -1; - } - -static char a2i(char ch, const char** src,int base,int* nump) - { - const char* p= *src; - int num=0; - int digit; - while ((digit=a2d(ch))>=0) { - if (digit>base) break; - num=num*base+digit; - ch=*p++; - } - *src=p; - *nump=num; - return ch; - } - -static void putchw(void* putp,putcf putf,int n, char z, char* bf) - { - char fc=z? '0' : ' '; - char ch; - char* p=bf; - while (*p++ && n > 0) - n--; - while (n-- > 0) - putf(putp,fc); - while ((ch= *bf++)) - putf(putp,ch); - } - -void tfp_format(void* putp,putcf putf,const char *fmt, va_list va) - { - char bf[12]; - - char ch; - - - while ((ch=*(fmt++))) { - if (ch!='%') - putf(putp,ch); - else { - char lz=0; -#ifdef PRINTF_LONG_SUPPORT - char lng=0; -#endif - int w=0; - ch=*(fmt++); - if (ch=='0') { - ch=*(fmt++); - lz=1; - } - if (ch>='0' && ch<='9') { - ch=a2i(ch,&fmt,10,&w); - } -#ifdef PRINTF_LONG_SUPPORT - if (ch=='l') { - ch=*(fmt++); - lng=1; - } -#endif - switch (ch) { - case 0: - goto abort; - case 'u' : { -#ifdef PRINTF_LONG_SUPPORT - if (lng) - uli2a(va_arg(va, unsigned long int),10,0,bf); - else -#endif - ui2a(va_arg(va, unsigned int),10,0,bf); - putchw(putp,putf,w,lz,bf); - break; - } - case 'd' : { -#ifdef PRINTF_LONG_SUPPORT - if (lng) - li2a(va_arg(va, unsigned long int),bf); - else -#endif - i2a(va_arg(va, int),bf); - putchw(putp,putf,w,lz,bf); - break; - } - case 'x': case 'X' : -#ifdef PRINTF_LONG_SUPPORT - if (lng) - uli2a(va_arg(va, unsigned long int),16,(ch=='X'),bf); - else -#endif - ui2a(va_arg(va, unsigned int),16,(ch=='X'),bf); - putchw(putp,putf,w,lz,bf); - break; - case 'c' : - putf(putp,(char)(va_arg(va, int))); - break; - case 's' : - putchw(putp,putf,w,0,va_arg(va, char*)); - break; - case '%' : - putf(putp,ch); - default: - break; - } - } - } - abort:; - } - - -void init_printf(void* putp,void (*putf) (void*,char)) - { - stdout_putf=putf; - stdout_putp=putp; - } - -void tfp_printf(const char *fmt, ...) - { - va_list va; - va_start(va,fmt); - tfp_format(stdout_putp,stdout_putf,fmt,va); - va_end(va); - } - -static void putcp(void* p,char c) - { - *(*((char**)p))++ = c; - } - - - -void tfp_sprintf(char* s,const char *fmt, ...) - { - va_list va; - va_start(va,fmt); - tfp_format(&s,putcp,fmt,va); - putcp(&s,0); - va_end(va); - } - - +/* + * Copyright (c) 2004,2012 Kustaa Nyholm / SpareTimeLabs + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * Neither the name of the Kustaa Nyholm or SpareTimeLabs nor the names of its + * contributors may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + */ + +#include "printf.h" + +typedef void (*putcf) (void*,char); +static putcf stdout_putf; +static void* stdout_putp; + + +#ifdef PRINTF_LONG_SUPPORT + +static void uli2a(unsigned long int num, unsigned int base, int uc,char * bf) + { + int n=0; + unsigned int d=1; + while (num/d >= base) + d*=base; + while (d!=0) { + int dgt = num / d; + num%=d; + d/=base; + if (n || dgt>0|| d==0) { + *bf++ = dgt+(dgt<10 ? '0' : (uc ? 'A' : 'a')-10); + ++n; + } + } + *bf=0; + } + +static void li2a (long num, char * bf) + { + if (num<0) { + num=-num; + *bf++ = '-'; + } + uli2a(num,10,0,bf); + } + +#endif + +static void ui2a(unsigned int num, unsigned int base, int uc,char * bf) + { + int n=0; + unsigned int d=1; + while (num/d >= base) + d*=base; + while (d!=0) { + int dgt = num / d; + num%= d; + d/=base; + if (n || dgt>0 || d==0) { + *bf++ = dgt+(dgt<10 ? '0' : (uc ? 'A' : 'a')-10); + ++n; + } + } + *bf=0; + } + +static void i2a (int num, char * bf) + { + if (num<0) { + num=-num; + *bf++ = '-'; + } + ui2a(num,10,0,bf); + } + +static int a2d(char ch) + { + if (ch>='0' && ch<='9') + return ch-'0'; + else if (ch>='a' && ch<='f') + return ch-'a'+10; + else if (ch>='A' && ch<='F') + return ch-'A'+10; + else return -1; + } + +static char a2i(char ch, const char** src,int base,int* nump) + { + const char* p= *src; + int num=0; + int digit; + while ((digit=a2d(ch))>=0) { + if (digit>base) break; + num=num*base+digit; + ch=*p++; + } + *src=p; + *nump=num; + return ch; + } + +static void putchw(void* putp,putcf putf,int n, char z, char* bf) + { + char fc=z? '0' : ' '; + char ch; + char* p=bf; + while (*p++ && n > 0) + n--; + while (n-- > 0) + putf(putp,fc); + while ((ch= *bf++)) + putf(putp,ch); + } + +void tfp_format(void* putp,putcf putf,const char *fmt, va_list va) + { + char bf[12]; + + char ch; + + + while ((ch=*(fmt++))) { + if (ch!='%') + putf(putp,ch); + else { + char lz=0; +#ifdef PRINTF_LONG_SUPPORT + char lng=0; +#endif + int w=0; + ch=*(fmt++); + if (ch=='0') { + ch=*(fmt++); + lz=1; + } + if (ch>='0' && ch<='9') { + ch=a2i(ch,&fmt,10,&w); + } +#ifdef PRINTF_LONG_SUPPORT + if (ch=='l') { + ch=*(fmt++); + lng=1; + } +#endif + switch (ch) { + case 0: + goto abort; + case 'u' : { +#ifdef PRINTF_LONG_SUPPORT + if (lng) + uli2a(va_arg(va, unsigned long int),10,0,bf); + else +#endif + ui2a(va_arg(va, unsigned int),10,0,bf); + putchw(putp,putf,w,lz,bf); + break; + } + case 'd' : { +#ifdef PRINTF_LONG_SUPPORT + if (lng) + li2a(va_arg(va, unsigned long int),bf); + else +#endif + i2a(va_arg(va, int),bf); + putchw(putp,putf,w,lz,bf); + break; + } + case 'x': case 'X' : +#ifdef PRINTF_LONG_SUPPORT + if (lng) + uli2a(va_arg(va, unsigned long int),16,(ch=='X'),bf); + else +#endif + ui2a(va_arg(va, unsigned int),16,(ch=='X'),bf); + putchw(putp,putf,w,lz,bf); + break; + case 'c' : + putf(putp,(char)(va_arg(va, int))); + break; + case 's' : + putchw(putp,putf,w,0,va_arg(va, char*)); + break; + case '%' : + putf(putp,ch); + default: + break; + } + } + } + abort:; + } + + +void init_printf(void* putp,void (*putf) (void*,char)) + { + stdout_putf=putf; + stdout_putp=putp; + } + +void tfp_printf(const char *fmt, ...) + { + va_list va; + va_start(va,fmt); + tfp_format(stdout_putp,stdout_putf,fmt,va); + va_end(va); + } + +static void putcp(void* p,char c) + { + *(*((char**)p))++ = c; + } + + + +void tfp_sprintf(char* s,const char *fmt, ...) + { + va_list va; + va_start(va,fmt); + tfp_format(&s,putcp,fmt,va); + putcp(&s,0); + va_end(va); + } + + diff --git a/xilinx/general/sdk/common/printf.h b/xilinx/general/sdk/common/printf.h index 536f987de7..a04ed7fac5 100755 --- a/xilinx/general/sdk/common/printf.h +++ b/xilinx/general/sdk/common/printf.h @@ -1,124 +1,124 @@ -/* -File: printf.h - -Copyright (c) 2004,2012 Kustaa Nyholm / SpareTimeLabs - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -Redistributions of source code must retain the above copyright notice, this list -of conditions and the following disclaimer. - -Redistributions in binary form must reproduce the above copyright notice, this -list of conditions and the following disclaimer in the documentation and/or other -materials provided with the distribution. - -Neither the name of the Kustaa Nyholm or SpareTimeLabs nor the names of its -contributors may be used to endorse or promote products derived from this software -without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. - ----------------------------------------------------------------------- - -This library is realy just two files: 'printf.h' and 'printf.c'. - -They provide a simple and small (+200 loc) printf functionality to -be used in embedded systems. - -I've found them so usefull in debugging that I do not bother with a -debugger at all. - -They are distributed in source form, so to use them, just compile them -into your project. - -Two printf variants are provided: printf and sprintf. - -The formats supported by this implementation are: 'd' 'u' 'c' 's' 'x' 'X'. - -Zero padding and field width are also supported. - -If the library is compiled with 'PRINTF_SUPPORT_LONG' defined then the -long specifier is also -supported. Note that this will pull in some long math routines (pun intended!) -and thus make your executable noticably longer. - -The memory foot print of course depends on the target cpu, compiler and -compiler options, but a rough guestimate (based on a H8S target) is about -1.4 kB for code and some twenty 'int's and 'char's, say 60 bytes of stack space. -Not too bad. Your milage may vary. By hacking the source code you can -get rid of some hunred bytes, I'm sure, but personally I feel the balance of -functionality and flexibility versus code size is close to optimal for -many embedded systems. - -To use the printf you need to supply your own character output function, -something like : - -void putc ( void* p, char c) - { - while (!SERIAL_PORT_EMPTY) ; - SERIAL_PORT_TX_REGISTER = c; - } - -Before you can call printf you need to initialize it to use your -character output function with something like: - -init_printf(NULL,putc); - -Notice the 'NULL' in 'init_printf' and the parameter 'void* p' in 'putc', -the NULL (or any pointer) you pass into the 'init_printf' will eventually be -passed to your 'putc' routine. This allows you to pass some storage space (or -anything realy) to the character output function, if necessary. -This is not often needed but it was implemented like that because it made -implementing the sprintf function so neat (look at the source code). - -The code is re-entrant, except for the 'init_printf' function, so it -is safe to call it from interupts too, although this may result in mixed output. -If you rely on re-entrancy, take care that your 'putc' function is re-entrant! - -The printf and sprintf functions are actually macros that translate to -'tfp_printf' and 'tfp_sprintf'. This makes it possible -to use them along with 'stdio.h' printf's in a single source file. -You just need to undef the names before you include the 'stdio.h'. -Note that these are not function like macros, so if you have variables -or struct members with these names, things will explode in your face. -Without variadic macros this is the best we can do to wrap these -fucnction. If it is a problem just give up the macros and use the -functions directly or rename them. - -For further details see source code. - -regs Kusti, 23.10.2004 -*/ - - -#ifndef __TFP_PRINTF__ -#define __TFP_PRINTF__ - -#include - -void init_printf(void* putp,void (*putf) (void*,char)); - -void tfp_printf(const char *fmt, ...); -void tfp_sprintf(char* s,const char *fmt, ...); - -void tfp_format(void* putp,void (*putf) (void*,char),const char *fmt, va_list va); - -#define printf tfp_printf -#define sprintf tfp_sprintf - -#endif - - - +/* +File: printf.h + +Copyright (c) 2004,2012 Kustaa Nyholm / SpareTimeLabs + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +Redistributions of source code must retain the above copyright notice, this list +of conditions and the following disclaimer. + +Redistributions in binary form must reproduce the above copyright notice, this +list of conditions and the following disclaimer in the documentation and/or other +materials provided with the distribution. + +Neither the name of the Kustaa Nyholm or SpareTimeLabs nor the names of its +contributors may be used to endorse or promote products derived from this software +without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +---------------------------------------------------------------------- + +This library is realy just two files: 'printf.h' and 'printf.c'. + +They provide a simple and small (+200 loc) printf functionality to +be used in embedded systems. + +I've found them so usefull in debugging that I do not bother with a +debugger at all. + +They are distributed in source form, so to use them, just compile them +into your project. + +Two printf variants are provided: printf and sprintf. + +The formats supported by this implementation are: 'd' 'u' 'c' 's' 'x' 'X'. + +Zero padding and field width are also supported. + +If the library is compiled with 'PRINTF_SUPPORT_LONG' defined then the +long specifier is also +supported. Note that this will pull in some long math routines (pun intended!) +and thus make your executable noticably longer. + +The memory foot print of course depends on the target cpu, compiler and +compiler options, but a rough guestimate (based on a H8S target) is about +1.4 kB for code and some twenty 'int's and 'char's, say 60 bytes of stack space. +Not too bad. Your milage may vary. By hacking the source code you can +get rid of some hunred bytes, I'm sure, but personally I feel the balance of +functionality and flexibility versus code size is close to optimal for +many embedded systems. + +To use the printf you need to supply your own character output function, +something like : + +void putc ( void* p, char c) + { + while (!SERIAL_PORT_EMPTY) ; + SERIAL_PORT_TX_REGISTER = c; + } + +Before you can call printf you need to initialize it to use your +character output function with something like: + +init_printf(NULL,putc); + +Notice the 'NULL' in 'init_printf' and the parameter 'void* p' in 'putc', +the NULL (or any pointer) you pass into the 'init_printf' will eventually be +passed to your 'putc' routine. This allows you to pass some storage space (or +anything realy) to the character output function, if necessary. +This is not often needed but it was implemented like that because it made +implementing the sprintf function so neat (look at the source code). + +The code is re-entrant, except for the 'init_printf' function, so it +is safe to call it from interupts too, although this may result in mixed output. +If you rely on re-entrancy, take care that your 'putc' function is re-entrant! + +The printf and sprintf functions are actually macros that translate to +'tfp_printf' and 'tfp_sprintf'. This makes it possible +to use them along with 'stdio.h' printf's in a single source file. +You just need to undef the names before you include the 'stdio.h'. +Note that these are not function like macros, so if you have variables +or struct members with these names, things will explode in your face. +Without variadic macros this is the best we can do to wrap these +fucnction. If it is a problem just give up the macros and use the +functions directly or rename them. + +For further details see source code. + +regs Kusti, 23.10.2004 +*/ + + +#ifndef __TFP_PRINTF__ +#define __TFP_PRINTF__ + +#include + +void init_printf(void* putp,void (*putf) (void*,char)); + +void tfp_printf(const char *fmt, ...); +void tfp_sprintf(char* s,const char *fmt, ...); + +void tfp_format(void* putp,void (*putf) (void*,char),const char *fmt, va_list va); + +#define printf tfp_printf +#define sprintf tfp_sprintf + +#endif + + + diff --git a/xilinx/general/sdk/common/ssi_printf.c b/xilinx/general/sdk/common/ssi_printf.c index f95471c7b8..4b63686d1b 100644 --- a/xilinx/general/sdk/common/ssi_printf.c +++ b/xilinx/general/sdk/common/ssi_printf.c @@ -1,10 +1,10 @@ ////////////////////////////////////////////////////////////////////////////// // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. ////////////////////////////////////////////////////////////////////////////// @@ -32,7 +32,7 @@ void ssi_putc ( void* p, char c) { pp->tmp = 0; pp->tmpCnt = 0; } - + // Dual port ram buffer if enabled if ( pp->buffSize > 0 ) { //Xil_Out8(pp->buffBase+4+pp->buffPtr, c); @@ -44,17 +44,17 @@ void ssi_putc ( void* p, char c) { // Adjust pointer pp->buffPtr++; - if ( pp->buffPtr == (pp->buffSize-4) ) + if ( pp->buffPtr == (pp->buffSize-4) ) pp->buffPtr = 0; // Adjust total - if ( pp->buffTot < (pp->buffSize-4) ) + if ( pp->buffTot < (pp->buffSize-4) ) pp->buffTot++; // Update tracking Xil_Out32(pp->buffBase, pp->buffTot << 16 | pp->buffPtr); } - + } void ssi_printf_init(uint32_t buffBase, uint16_t buffSize) { diff --git a/xilinx/general/sdk/common/ssi_printf.h b/xilinx/general/sdk/common/ssi_printf.h index c28aa6402d..3ee37d6c1a 100644 --- a/xilinx/general/sdk/common/ssi_printf.h +++ b/xilinx/general/sdk/common/ssi_printf.h @@ -1,10 +1,10 @@ ////////////////////////////////////////////////////////////////////////////// // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. ////////////////////////////////////////////////////////////////////////////// From 832c9502fa05d46f97e0a3541c3507583c4b08d3 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 25 Sep 2023 14:01:09 -0700 Subject: [PATCH 30/45] exposing JUMBO_G generic to high level ETH wrapper level --- ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd | 2 ++ ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd | 2 ++ ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd | 2 ++ .../GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd | 2 ++ ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd | 2 ++ ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd | 2 ++ ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd | 2 ++ ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd | 2 ++ ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd | 2 ++ ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd | 2 ++ ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd | 2 ++ .../TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd | 2 ++ .../gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd | 2 ++ .../TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd | 2 ++ .../gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd | 2 ++ ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd | 2 ++ ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd | 2 ++ .../TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd | 2 ++ .../gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd | 2 ++ ethernet/XauiCore/gth7/rtl/XauiGth7.vhd | 2 ++ ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd | 2 ++ ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd | 2 ++ .../XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd | 2 ++ ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd | 2 ++ .../XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd | 2 ++ ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd | 2 ++ ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd | 2 ++ ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd | 2 ++ .../XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd | 2 ++ 29 files changed, 58 insertions(+) diff --git a/ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd b/ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd index c3bd67f0ea..1236b18b45 100644 --- a/ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd +++ b/ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd @@ -26,6 +26,7 @@ use surf.GigEthPkg.all; entity GigEthGth7 is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -170,6 +171,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PAUSE_512BITS_G => PAUSE_512BITS_C, PHY_TYPE_G => "GMII", diff --git a/ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd b/ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd index 94061d5503..b46cb01d4f 100644 --- a/ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd +++ b/ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd @@ -31,6 +31,7 @@ entity GigEthGth7Wrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- Clocking Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk @@ -166,6 +167,7 @@ begin U_GigEthGth7 : entity surf.GigEthGth7 generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd index 0312243ba9..1d1e2f86cd 100644 --- a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd +++ b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd @@ -26,6 +26,7 @@ use surf.GigEthPkg.all; entity GigEthGthUltraScale is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -182,6 +183,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PAUSE_512BITS_G => PAUSE_512BITS_C, PHY_TYPE_G => "GMII", diff --git a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd index 9d0620f54c..9b5b31138c 100644 --- a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd +++ b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd @@ -31,6 +31,7 @@ entity GigEthGthUltraScaleWrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- Clocking Configurations EXT_PLL_G : boolean := false; @@ -193,6 +194,7 @@ begin U_GigEthGthUltraScale : entity surf.GigEthGthUltraScale generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd index 8442c148f4..ad5168567e 100644 --- a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd +++ b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd @@ -26,6 +26,7 @@ use surf.GigEthPkg.all; entity GigEthGtp7 is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -224,6 +225,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PAUSE_512BITS_G => PAUSE_512BITS_C, PHY_TYPE_G => "GMII", diff --git a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd index 6cff4cf26e..bfab8912fd 100644 --- a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd +++ b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd @@ -31,6 +31,7 @@ entity GigEthGtp7Wrapper is TPD_G : time := 1 ns; SIMULATION_G : boolean := false; NUM_LANE_G : natural range 1 to 4 := 1; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- Clocking Configurations USE_GTREFCLK_G : boolean := false; @@ -221,6 +222,7 @@ begin U_GigEthGtp7 : entity surf.GigEthGtp7 generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd b/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd index 5d28d3a8c5..59378c1ec8 100644 --- a/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd +++ b/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd @@ -27,6 +27,7 @@ use surf.GigEthPkg.all; entity GigEthGtx7 is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; SYNTH_MODE_G : string := "inferred"; -- AXI-Lite Configurations @@ -235,6 +236,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PAUSE_512BITS_G => PAUSE_512BITS_C, PHY_TYPE_G => "GMII", diff --git a/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd b/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd index 84639c0a2d..e593e34331 100644 --- a/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd +++ b/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd @@ -31,6 +31,7 @@ entity GigEthGtx7Wrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- Clocking Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk @@ -166,6 +167,7 @@ begin U_GigEthGtx7 : entity surf.GigEthGtx7 generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd b/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd index 397551aeb8..b09e32ac1c 100644 --- a/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd +++ b/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd @@ -25,6 +25,7 @@ use surf.GigEthPkg.all; entity GigEthLvdsUltraScale is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXIL_REG_G : boolean := false; @@ -156,6 +157,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PAUSE_512BITS_G => PAUSE_512BITS_C, PHY_TYPE_G => "GMII", diff --git a/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd b/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd index dc484dc008..3b3b2ebb1e 100644 --- a/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd +++ b/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd @@ -26,6 +26,7 @@ use surf.EthMacPkg.all; entity TenGigEthGth7 is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -208,6 +209,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PHY_TYPE_G => "XGMII", PRIM_CONFIG_G => AXIS_CONFIG_G) diff --git a/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd b/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd index f9392605a5..6e00f4454d 100644 --- a/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd +++ b/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd @@ -28,6 +28,7 @@ entity TenGigEthGth7Wrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- QUAD PLL Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk @@ -126,6 +127,7 @@ begin TenGigEthGth7_Inst : entity surf.TenGigEthGth7 generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd index dc5850a151..4a5e2b891d 100644 --- a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd @@ -25,6 +25,7 @@ use surf.EthMacPkg.all; entity TenGigEthGthUltraScale is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -234,6 +235,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, FIFO_ADDR_WIDTH_G => 12, -- single 4K UltraRAM SYNTH_MODE_G => "xpm", diff --git a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd index fcb7ec41c4..33945f6105 100644 --- a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd @@ -28,6 +28,7 @@ entity TenGigEthGthUltraScaleWrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- QUAD PLL Configurations EXT_REF_G : boolean := false; @@ -143,6 +144,7 @@ begin TenGigEthGthUltraScale_Inst : entity surf.TenGigEthGthUltraScale generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd index 9d740f47fe..3eab811909 100644 --- a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd @@ -26,6 +26,7 @@ use surf.EthMacPkg.all; entity TenGigEthGthUltraScale is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -254,6 +255,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PHY_TYPE_G => "XGMII", PRIM_CONFIG_G => AXIS_CONFIG_G) diff --git a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd index 69d69f5274..3c1f7f72f5 100644 --- a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd @@ -28,6 +28,7 @@ entity TenGigEthGthUltraScaleWrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- QUAD PLL Configurations EXT_REF_G : boolean := false; @@ -146,6 +147,7 @@ begin TenGigEthGthUltraScale_Inst : entity surf.TenGigEthGthUltraScale generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd b/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd index 57dd3a9ca5..d21ee53c66 100644 --- a/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd +++ b/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd @@ -26,6 +26,7 @@ use surf.EthMacPkg.all; entity TenGigEthGtx7 is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -234,6 +235,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PHY_TYPE_G => "XGMII", PRIM_CONFIG_G => AXIS_CONFIG_G) diff --git a/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd b/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd index d4b9894021..afe0f8903b 100644 --- a/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd +++ b/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd @@ -28,6 +28,7 @@ entity TenGigEthGtx7Wrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- QUAD PLL Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk @@ -134,6 +135,7 @@ begin TenGigEthGtx7_Inst : entity surf.TenGigEthGtx7 generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd index f4dc127e38..dc8ebe3697 100644 --- a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd +++ b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd @@ -25,6 +25,7 @@ use surf.EthMacPkg.all; entity TenGigEthGtyUltraScale is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -234,6 +235,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, FIFO_ADDR_WIDTH_G => 12, -- single 4K UltraRAM SYNTH_MODE_G => "xpm", diff --git a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd index 48aaab8cf4..948d3e528d 100644 --- a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd +++ b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd @@ -29,6 +29,7 @@ entity TenGigEthGtyUltraScaleWrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- QUAD PLL Configurations QPLL_REFCLK_SEL_G : slv(2 downto 0) := "001"; @@ -140,6 +141,7 @@ begin TenGigEthGtyUltraScale_Inst : entity surf.TenGigEthGtyUltraScale generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/XauiCore/gth7/rtl/XauiGth7.vhd b/ethernet/XauiCore/gth7/rtl/XauiGth7.vhd index 41e2cf60be..13e17834c0 100644 --- a/ethernet/XauiCore/gth7/rtl/XauiGth7.vhd +++ b/ethernet/XauiCore/gth7/rtl/XauiGth7.vhd @@ -26,6 +26,7 @@ use surf.EthMacPkg.all; entity XauiGth7 is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -92,6 +93,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PHY_TYPE_G => "XGMII", PRIM_CONFIG_G => AXIS_CONFIG_G) diff --git a/ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd b/ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd index a248e2e78a..53fd5fc385 100644 --- a/ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd +++ b/ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd @@ -29,6 +29,7 @@ use unisim.vcomponents.all; entity XauiGth7Wrapper is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- QUAD PLL Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk @@ -95,6 +96,7 @@ begin XauiGth7_Inst : entity surf.XauiGth7 generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd b/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd index a03a032408..a5ea828b06 100644 --- a/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd +++ b/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd @@ -28,6 +28,7 @@ use unisim.vcomponents.all; entity XauiGthUltraScale is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- XAUI Configurations REF_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz @@ -202,6 +203,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, FIFO_ADDR_WIDTH_G => 12, -- single 4K UltraRAM SYNTH_MODE_G => "xpm", diff --git a/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd b/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd index fe0d60bf73..8e984b8284 100644 --- a/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd +++ b/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd @@ -29,6 +29,7 @@ use unisim.vcomponents.all; entity XauiGthUltraScaleWrapper is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; EN_WDT_G : boolean := false; EXT_REF_G : boolean := false; @@ -139,6 +140,7 @@ begin XauiGthUltraScale_Inst : entity surf.XauiGthUltraScale generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd b/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd index d30a8d8fc4..7e1e90cdec 100644 --- a/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd +++ b/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd @@ -29,6 +29,7 @@ use unisim.vcomponents.all; entity XauiGthUltraScale is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -195,6 +196,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PHY_TYPE_G => "XGMII", PRIM_CONFIG_G => AXIS_CONFIG_G) diff --git a/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd b/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd index e199d11fb3..a560bdf56c 100644 --- a/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd +++ b/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd @@ -29,6 +29,7 @@ use unisim.vcomponents.all; entity XauiGthUltraScaleWrapper is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; EN_WDT_G : boolean := false; EXT_REF_G : boolean := false; @@ -139,6 +140,7 @@ begin XauiGthUltraScale_Inst : entity surf.XauiGthUltraScale generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd b/ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd index 90972f89f7..0ff5e63c0e 100644 --- a/ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd +++ b/ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd @@ -26,6 +26,7 @@ use surf.EthMacPkg.all; entity XauiGtx7 is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -92,6 +93,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PHY_TYPE_G => "XGMII", PRIM_CONFIG_G => AXIS_CONFIG_G) diff --git a/ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd b/ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd index dcaa5c867e..f7ffdd41cf 100644 --- a/ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd +++ b/ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd @@ -29,6 +29,7 @@ use unisim.vcomponents.all; entity XauiGtx7Wrapper is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- QUAD PLL Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk @@ -95,6 +96,7 @@ begin XauiGtx7_Inst : entity surf.XauiGtx7 generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd b/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd index 7480e5092e..aa62e3f26e 100644 --- a/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd +++ b/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd @@ -28,6 +28,7 @@ use unisim.vcomponents.all; entity XauiGtyUltraScale is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- XAUI Configurations REF_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz @@ -202,6 +203,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, FIFO_ADDR_WIDTH_G => 12, -- single 4K UltraRAM SYNTH_MODE_G => "xpm", diff --git a/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd b/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd index 9f9edac47e..4100ce704d 100644 --- a/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd +++ b/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd @@ -31,6 +31,7 @@ entity XauiGtyUltraScaleWrapper is TPD_G : time := 1 ns; EN_WDT_G : boolean := false; STABLE_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -134,6 +135,7 @@ begin XauiGtyUltraScale_Inst : entity surf.XauiGtyUltraScale generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, From f85aebb9b9f5058f41033107ad19d5ac0b019356 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Wed, 27 Sep 2023 10:13:47 -0700 Subject: [PATCH 31/45] Updating AxiStreamRingBuffer.vhd adding support for COMMON_CLK_G when (dataClk=axilClk) case --- axi/axi-stream/rtl/AxiStreamRingBuffer.vhd | 3 +++ 1 file changed, 3 insertions(+) diff --git a/axi/axi-stream/rtl/AxiStreamRingBuffer.vhd b/axi/axi-stream/rtl/AxiStreamRingBuffer.vhd index 07747931dd..85857fa4ef 100644 --- a/axi/axi-stream/rtl/AxiStreamRingBuffer.vhd +++ b/axi/axi-stream/rtl/AxiStreamRingBuffer.vhd @@ -29,6 +29,7 @@ entity AxiStreamRingBuffer is RST_ASYNC_G : boolean := false; SYNTH_MODE_G : string := "inferred"; MEMORY_TYPE_G : string := "block"; + COMMON_CLK_G : boolean := false; -- true if dataClk=axilClk DATA_BYTES_G : positive := 16; RAM_ADDR_WIDTH_G : positive := 9; -- AXI Stream Configurations @@ -172,6 +173,7 @@ begin U_Ram : entity surf.SimpleDualPortRamXpm generic map ( TPD_G => TPD_G, + COMMON_CLK_G => COMMON_CLK_G, MEMORY_TYPE_G => MEMORY_TYPE_G, READ_LATENCY_G => 2, DATA_WIDTH_G => 8*DATA_BYTES_G, @@ -193,6 +195,7 @@ begin U_Ram : entity surf.SimpleDualPortRamAlteraMf generic map ( TPD_G => TPD_G, + COMMON_CLK_G => COMMON_CLK_G, MEMORY_TYPE_G => MEMORY_TYPE_G, READ_LATENCY_G => 2, DATA_WIDTH_G => 8*DATA_BYTES_G, From 19890f25ac7aba5418c41592f95e9d2dfd08280f Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Wed, 27 Sep 2023 12:36:50 -0700 Subject: [PATCH 32/45] revert PR #115 change on Idelaye3Wrapper.vhd This change breaks builds that using MODE=COUNT for the IDELAY --- xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd b/xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd index 06e93d2fec..f8304daa25 100644 --- a/xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd +++ b/xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd @@ -37,8 +37,7 @@ entity Idelaye3Wrapper is IS_RST_INVERTED : bit := '0'; -- Optional inversion for RST REFCLK_FREQUENCY : real := 300.0; -- IDELAYCTRL clock input frequency in MHz (200.0-2667.0) SIM_DEVICE : string := "ULTRASCALE"; -- Set the device version (ULTRASCALE, ULTRASCALE_PLUS) - UPDATE_MODE : string := "ASYNC"; - IODELAY_GROUP_G : string := "DLYGRP_C"); -- Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC) + UPDATE_MODE : string := "ASYNC"); -- Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC) port ( BUSY : out sl; -- 1-bit output: Patch module is busy CASC_OUT : out sl; -- 1-bit output: Cascade delay output to ODELAY input cascade @@ -63,9 +62,6 @@ architecture rtl of Idelaye3Wrapper is signal patchCntValue : slv(8 downto 0); signal patchLoad : sl; - attribute IODELAY_GROUP : string; - attribute IODELAY_GROUP of U_IDELAYE3 : label is IODELAY_GROUP_G; - begin CNTVALUEOUT <= currentCntValue; From 6607e78f5621e988bb6e39208860f09a640cc041 Mon Sep 17 00:00:00 2001 From: lorenzrota Date: Wed, 11 Oct 2023 11:20:26 -0700 Subject: [PATCH 33/45] Added rst to Scrambler --- protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd index a7dee767d5..b09542822f 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd @@ -56,6 +56,7 @@ architecture mapping of Pgp4TxLiteWrapper is signal pgpTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal pgpTxSlave : AxiStreamSlaveType; + signal rstL : sl; begin @@ -89,11 +90,13 @@ begin remRxFifoCtrl(0)=> AXI_STREAM_CTRL_UNUSED_C, remRxLinkReady => '1', -- PHY interface - phyTxActive => '1', + phyTxActive => rstL, phyTxReady => phyTxReady, phyTxValid => phyTxValid, phyTxStart => open, phyTxData => phyTxData(63 downto 0), phyTxHeader => phyTxData(65 downto 64)); + rstL <= not(rst); + end architecture mapping; From 6d72db9457e2ff62a0e83b52dc312accd529d1a7 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 12 Oct 2023 11:17:24 -0700 Subject: [PATCH 34/45] xilinx/_RfTile.py update powerOnSequenceSteps enum only defined for 4-bits (not 8-bits) --- python/surf/xilinx/_RfTile.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/python/surf/xilinx/_RfTile.py b/python/surf/xilinx/_RfTile.py index fed32f9872..cd16bdfef7 100644 --- a/python/surf/xilinx/_RfTile.py +++ b/python/surf/xilinx/_RfTile.py @@ -59,7 +59,7 @@ def __init__( name = 'RestartStateEnd', description = 'End state for power-on sequence', offset = 0x0008, - bitSize = 8, + bitSize = 4, bitOffset = 0, mode = 'RW', enum = powerOnSequenceSteps, @@ -69,7 +69,7 @@ def __init__( name = 'RestartStateStart', description = 'Start state for power-on sequence', offset = 0x0008, - bitSize = 8, + bitSize = 4, bitOffset = 8, mode = 'RW', enum = powerOnSequenceSteps, @@ -79,7 +79,7 @@ def __init__( name = 'CurrentState', description = 'Current state register', offset = 0x000C, - bitSize = 8, + bitSize = 4, bitOffset = 0, mode = 'RO', pollInterval = 1, From 3afe17a74db6bb10f728e29f9b63fd6fc314e40a Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 13 Oct 2023 15:26:31 -0700 Subject: [PATCH 35/45] Pgp4TxLiteWrapper.vhd clean up whitespace removal --- protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd index b09542822f..2eb515de10 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd @@ -88,7 +88,7 @@ begin locRxFifoCtrl(0)=> AXI_STREAM_CTRL_UNUSED_C, locRxLinkReady => '1', remRxFifoCtrl(0)=> AXI_STREAM_CTRL_UNUSED_C, - remRxLinkReady => '1', + remRxLinkReady => '1', -- PHY interface phyTxActive => rstL, phyTxReady => phyTxReady, From be40ef9b10ecd96387ae0e071afd32a1f364f4ac Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 24 Oct 2023 12:23:49 -0700 Subject: [PATCH 36/45] Enhancements to XADC rogue Device --- python/surf/xilinx/_Xadc.py | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/python/surf/xilinx/_Xadc.py b/python/surf/xilinx/_Xadc.py index eebc5cd4fd..38b675a7d3 100644 --- a/python/surf/xilinx/_Xadc.py +++ b/python/surf/xilinx/_Xadc.py @@ -22,12 +22,17 @@ def __init__(self, description = "AXI-Lite XADC for Xilinx 7 Series (Refer to PG091 & PG019)", auxChannels = 0, zynq = False, + simpleViewList = ["Temperature", "VccInt", "VccAux", "VccBram"], + pollInterval = 5, **kwargs): super().__init__(description=description, **kwargs) if isinstance(auxChannels, int): auxChannels = list(range(auxChannels)) + self.simpleViewList = simpleViewList + self.simpleViewList.append('enable') + def addPair(name, offset, bitSize, units, bitOffset, description, function, pollInterval=0): self.add(pr.RemoteVariable( name = ("Raw"+name), @@ -331,6 +336,8 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll variable=self.AuxRaw[ch], linkedGet=self.convAuxVoltage)) + self.simpleViewList.append(f'Aux[{ch}]') + if (zynq): addPair( name = 'VccpInt', @@ -610,5 +617,5 @@ def simpleView(self): # Hide all the variable self.hideVariables(hidden=True) # Then unhide the most interesting ones - vars = ["enable", "Temperature", "VccInt", "VccAux", "VccBram"] + vars = self.simpleViewList self.hideVariables(hidden=False, variables=vars) From bef90149d9fa6324558f35425b81352d90e02021 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 24 Oct 2023 21:45:58 -0700 Subject: [PATCH 37/45] Add paramatized pollInterval --- python/surf/xilinx/_Xadc.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/python/surf/xilinx/_Xadc.py b/python/surf/xilinx/_Xadc.py index 38b675a7d3..a53c99cefd 100644 --- a/python/surf/xilinx/_Xadc.py +++ b/python/surf/xilinx/_Xadc.py @@ -61,7 +61,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "degC", function = self.convTemp, - pollInterval = 5, + pollInterval = pollInterval, description = """ The result of the on-chip temperature sensor measurement is stored in this location. The data is MSB justified in the @@ -121,7 +121,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = """ The result of the on-chip VccInt supply monitor measurement is stored at this location. The data is MSB justified in the @@ -169,7 +169,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = """ The result of the on-chip VccAux supply monitor measurement is stored at this location. The data is MSB justified in the @@ -219,7 +219,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = """ The result of the on-chip VccBram supply monitor measurement is stored at this location. The data is MSB justified in the From f72491daae030ae85249289941a31a1a7b7defea Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 31 Oct 2023 20:05:58 -0700 Subject: [PATCH 38/45] adding MtsAdcSync/MtsDacSync --- python/surf/xilinx/_RfDataConverter.py | 36 ++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/python/surf/xilinx/_RfDataConverter.py b/python/surf/xilinx/_RfDataConverter.py index f70e61d4fb..b5186261c3 100644 --- a/python/surf/xilinx/_RfDataConverter.py +++ b/python/surf/xilinx/_RfDataConverter.py @@ -125,6 +125,42 @@ def __init__( expand = False, )) + for i in range(2): + self.add(pr.RemoteVariable( + name = f'MtsFifoCtrl[{i}]', + description = 'index[0] is MtsFifoCtrlADC, index[1] is MtsFifoCtrlDAC', + offset = 0x0010+4*i, + bitSize = 2, + bitOffset = 0, + mode = 'RW', + hidden = True, + )) + + self.add(pr.RemoteVariable( + name = 'MtsSysRefEnable', + offset = 0x6000+0x1C00+(0x24<<2), # XRFDC_DAC_TILE_DRP_ADDR(0) + XRFDC_HSCOM_ADDR offsets + XRFDC_MTS_SRCAP_T1 + bitSize = 1, + bitOffset = 10, # XRFDC_MTS_SRCAP_EN_TRX_M=0x0400 + mode = 'RW', + hidden = True, + )) + + def MtsAdcSync(self): + # Disable the FIFOs + self.MtsFifoCtrl[0].set(0x2) + # Enable SysRef Rx + self.MtsSysRefEnable.set(1) + # Disable the FIFOs + self.MtsFifoCtrl[0].set(0x3) + + def MtsDacSync(self): + # Disable the FIFOs + self.MtsFifoCtrl[1].set(0x2) + # Enable SysRef Rx + self.MtsSysRefEnable.set(1) + # Disable the FIFOs + self.MtsFifoCtrl[1].set(0x3) + def Init(self, dynamicNco=False): # Useful pointers From 0d8745f507738c05069d5562844f67974c3f8fc8 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 2 Nov 2023 10:30:08 -0700 Subject: [PATCH 39/45] Lmx2594.py Update turn off SYNC after the stable state --- python/surf/devices/ti/_Lmx2594.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/python/surf/devices/ti/_Lmx2594.py b/python/surf/devices/ti/_Lmx2594.py index 6ad9bd6a11..ab225e960a 100644 --- a/python/surf/devices/ti/_Lmx2594.py +++ b/python/surf/devices/ti/_Lmx2594.py @@ -257,3 +257,8 @@ def LoadCodeLoaderHexFile(arg): # 6. Program register R0 one additional time with FCAL_EN = 1 to ensure that the VCO calibration runs from a stable state. self.DataBlock.set(value=(data|0x8), index=0, write=True) + + # Turn off the SYNC after the stable state + self.DataBlock.set(value=0x0000, index=0x22, write=True) + self.DataBlock.set(value=0x0780, index=0x24, write=True) + From c7ae2a989089762af47554ae395511647ec9fb18 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 2 Nov 2023 16:01:38 -0700 Subject: [PATCH 40/45] bug fix for the LoadCodeLoaderHexFile() function --- python/surf/devices/ti/_Lmx2594.py | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/python/surf/devices/ti/_Lmx2594.py b/python/surf/devices/ti/_Lmx2594.py index ab225e960a..212f4a1b17 100644 --- a/python/surf/devices/ti/_Lmx2594.py +++ b/python/surf/devices/ti/_Lmx2594.py @@ -227,18 +227,19 @@ def addLinkVariable(name, description, offset, bitSize, mode, bitOffset=0, pollI @self.command(description='Load the CodeLoader .HEX file',value='',) def LoadCodeLoaderHexFile(arg): + self.DataBlock.set(value=0x2410,index=0, write=True) # MUXOUT_LD_SEL=readback + ################################################################## # For the most reliable programming, TI recommends this procedure: ################################################################## # 1. Apply power to device. - reg = self.DataBlock.get(index=0, read=True) # 2. Program RESET = 1 to reset registers. - self.DataBlock.set(value=(reg|0x2), index=0, write=True) + self.DataBlock.set(value=0x2412, index=0, write=True) # 3. Program RESET = 0 to remove reset. - self.DataBlock.set(value=(reg&0xFFFD), index=0, write=True) + self.DataBlock.set(value=0x2410, index=0, write=True) # 4. Program registers as shown in the register map in REVERSE order from highest to lowest. with open(arg, 'r') as ifd: @@ -250,15 +251,9 @@ def LoadCodeLoaderHexFile(arg): # print( f'addr={addr}, data={hex(data)}' ) self.DataBlock.set(value=data, index=addr, write=True) - self.DataBlock.set(value=data, index=addr, write=True) - # 5. Wait 10 ms. time.sleep(0.1) # 6. Program register R0 one additional time with FCAL_EN = 1 to ensure that the VCO calibration runs from a stable state. - self.DataBlock.set(value=(data|0x8), index=0, write=True) - - # Turn off the SYNC after the stable state - self.DataBlock.set(value=0x0000, index=0x22, write=True) - self.DataBlock.set(value=0x0780, index=0x24, write=True) - + self.DataBlock.set(value=data&0xFFFB, index=addr, write=True) + time.sleep(0.1) From 62f68a1af4e76ec3d344ae82fce2084908a95698 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 3 Nov 2023 11:03:21 -0700 Subject: [PATCH 41/45] updating microblaze/ruckus.tcl for Vivado 2023.2 Vivado bug for .bd not resolved yet --- xilinx/general/microblaze/ruckus.tcl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/xilinx/general/microblaze/ruckus.tcl b/xilinx/general/microblaze/ruckus.tcl index e9b79adb2e..65e47b3310 100644 --- a/xilinx/general/microblaze/ruckus.tcl +++ b/xilinx/general/microblaze/ruckus.tcl @@ -19,7 +19,8 @@ if { [info exists ::env(VITIS_SRC_PATH)] != 1 } { loadSource -lib surf -path "$::DIR_PATH/generate/MicroblazeBasicCoreWrapper.vhd" # Load the .bd file - if { $::env(VIVADO_VERSION) == 2023.1 || + if { $::env(VIVADO_VERSION) == 2023.2 || + $::env(VIVADO_VERSION) == 2023.1 || $::env(VIVADO_VERSION) == 2022.2 } { puts "\nVivado v$::env(VIVADO_VERSION) not supported for general/microblaze\n" exit -1 From db6cabc2259aa7dd70d4441c1261eed4b6aacf23 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 7 Nov 2023 08:58:15 -0800 Subject: [PATCH 42/45] Updating submodule lock for Vivado 2023.2 support --- ruckus.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ruckus.tcl b/ruckus.tcl index 6238316e6b..caa5da374f 100644 --- a/ruckus.tcl +++ b/ruckus.tcl @@ -3,7 +3,7 @@ source $::env(RUCKUS_PROC_TCL) # Check for submodule tagging if { [info exists ::env(OVERRIDE_SUBMODULE_LOCKS)] != 1 || $::env(OVERRIDE_SUBMODULE_LOCKS) == 0 } { - if { [SubmoduleCheck {ruckus} {4.8.4} ] < 0 } {exit -1} + if { [SubmoduleCheck {ruckus} {4.9.0} ] < 0 } {exit -1} } else { puts "\n\n*********************************************************" puts "OVERRIDE_SUBMODULE_LOCKS != 0" From abbe0dfeb19d9b2e49ff6ebdcb46e69afc41a7a6 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 9 Nov 2023 09:47:25 -0800 Subject: [PATCH 43/45] Update Makefile ### Description - Setting the python to explicitly to python3 --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 804aff4afe..586f1cf47b 100644 --- a/Makefile +++ b/Makefile @@ -34,7 +34,7 @@ GHDLFLAGS = --workdir=$(OUT_DIR) --ieee=synopsys -fexplicit -frelaxed-rules --w include $(RUCKUS_DIR)/system_shared.mk # Override system_shared.mk build string -export BUILD_SVR_TYPE = $(shell python -m platform) +export BUILD_SVR_TYPE = $(shell python3 -m platform) export GHDL_VERSION = $(shell ghdl -v 2>&1 | head -n 1) export BUILD_STRING = $(PROJECT): $(GHDL_VERSION), $(BUILD_SYS_NAME) ($(BUILD_SVR_TYPE)), Built $(BUILD_DATE) by $(BUILD_USER) From ba3920864ab0a5bb672da946f8b27afb9c6596be Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Wed, 29 Nov 2023 08:53:46 -0800 Subject: [PATCH 44/45] Pgp2bAxi.vhd Enchancement adding TxDiffCtrl, TxPreCursor, andn TxPostCursor registers --- protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd | 24 +++++++++++++++++++++++ python/surf/protocols/pgp/_Pgp2bAxi.py | 24 +++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd index 42602b5c9e..bcc5291302 100644 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd @@ -55,6 +55,11 @@ entity Pgp2bAxi is statusWord : out slv(63 downto 0); statusSend : out sl; + -- Debug Interface (axilClk domain) + txDiffCtrl : out slv(4 downto 0); + txPreCursor : out slv(4 downto 0); + txPostCursor : out slv(4 downto 0); + -- AXI-Lite Register Interface (axilClk domain) axilClk : in sl; axilRst : in sl; @@ -90,6 +95,9 @@ architecture structure of Pgp2bAxi is signal syncFlowCntlDis : sl; type RegType is record + txDiffCtrl : slv(4 downto 0); + txPreCursor : slv(4 downto 0); + txPostCursor : slv(4 downto 0); flush : sl; resetTx : sl; resetRx : sl; @@ -105,6 +113,9 @@ architecture structure of Pgp2bAxi is end record RegType; constant REG_INIT_C : RegType := ( + txDiffCtrl => "11111", + txPreCursor => "00111", + txPostCursor => "01111", flush => '0', resetTx => '0', resetRx => '0', @@ -566,6 +577,12 @@ begin v.autoStatus := axilWriteMaster.wdata(0); when X"18" => v.flowCntlDis := ite(WRITE_EN_G, axilWriteMaster.wdata(0), '0'); + when X"1C" => + if WRITE_EN_G then + v.txDiffCtrl := axilWriteMaster.wdata(4 downto 0); + v.txPreCursor := axilWriteMaster.wdata(9 downto 5); + v.txPostCursor := axilWriteMaster.wdata(14 downto 10); + end if; when others => null; end case; @@ -595,6 +612,10 @@ begin v.axilReadSlave.rdata(0) := r.autoStatus; when X"18" => v.axilReadSlave.rdata(0) := r.flowCntlDis; + when X"1C" => + v.axilReadSlave.rdata(4 downto 0) := r.txDiffCtrl; + v.axilReadSlave.rdata(9 downto 5) := r.txPreCursor; + v.axilReadSlave.rdata(14 downto 10) := r.txPostCursor; when X"20" => v.axilReadSlave.rdata(0) := rxStatusSync.phyRxReady; v.axilReadSlave.rdata(1) := txStatusSync.phyTxReady; @@ -671,6 +692,9 @@ begin -- Outputs axilReadSlave <= r.axilReadSlave; axilWriteSlave <= r.axilWriteSlave; + txDiffCtrl <= r.txDiffCtrl; + txPreCursor <= r.txPreCursor; + txPostCursor <= r.txPostCursor; end process; diff --git a/python/surf/protocols/pgp/_Pgp2bAxi.py b/python/surf/protocols/pgp/_Pgp2bAxi.py index cbfda5f6b0..34a53ecb7f 100644 --- a/python/surf/protocols/pgp/_Pgp2bAxi.py +++ b/python/surf/protocols/pgp/_Pgp2bAxi.py @@ -73,6 +73,30 @@ def __init__(self, base = pr.Bool, )) + self.add(pr.RemoteVariable( + name = "TxDiffCtrl", + offset = 0x1C, + bitSize = 5, + bitOffset = 0, + mode = "RW", + )) + + self.add(pr.RemoteVariable( + name = "TxPreCursor", + offset = 0x1C, + bitSize = 5, + bitOffset = 5, + mode = "RW", + )) + + self.add(pr.RemoteVariable( + name = "TxPostCursor", + offset = 0x1C, + bitSize = 5, + bitOffset = 10, + mode = "RW", + )) + self.add(pr.RemoteVariable( name = "RxPhyReady", offset = 0x20, From 35e59edb4da7ddf14f8c56fd213c635cb35cfb2b Mon Sep 17 00:00:00 2001 From: Agustin Romero <89935000+aer7@users.noreply.github.com> Date: Thu, 25 Jan 2024 12:20:50 -0800 Subject: [PATCH 45/45] Fix link variable call --- python/surf/ethernet/udp/__init__.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/python/surf/ethernet/udp/__init__.py b/python/surf/ethernet/udp/__init__.py index 910c7db174..234b17c885 100644 --- a/python/surf/ethernet/udp/__init__.py +++ b/python/surf/ethernet/udp/__init__.py @@ -21,7 +21,7 @@ def getPortValue(var): def setPortValue(var, value, write): newValue = int.from_bytes(value.to_bytes(2, byteorder='little'), byteorder='big', signed=False) - var.dependencies[0].set(newValue,write) + var.dependencies[0].set(newValue,write=write) def getIpValue(var): x = var.dependencies[0].value() @@ -30,7 +30,7 @@ def getIpValue(var): def setIpValue(var, value, write): x = int(ipaddress.IPv4Address(value)) newValue = int.from_bytes(x.to_bytes(4, byteorder='little'), byteorder='big', signed=False) - var.dependencies[0].set(newValue,write) + var.dependencies[0].set(newValue,write=write) def getMacValue(var): x = var.dependencies[0].value() @@ -41,4 +41,5 @@ def setMacValue(var, value, write): if( len(x) == 6): x = [int(i,16) for i in x] newValue = ( '0x%02x%02x%02x%02x%02x%02x' % (x[5],x[4],x[3],x[2],x[1],x[0]) ) - var.dependencies[0].set(int(newValue,16),write) + var.dependencies[0].set(int(newValue,16),write=write) +