diff --git a/Makefile b/Makefile index 804aff4afe..586f1cf47b 100644 --- a/Makefile +++ b/Makefile @@ -34,7 +34,7 @@ GHDLFLAGS = --workdir=$(OUT_DIR) --ieee=synopsys -fexplicit -frelaxed-rules --w include $(RUCKUS_DIR)/system_shared.mk # Override system_shared.mk build string -export BUILD_SVR_TYPE = $(shell python -m platform) +export BUILD_SVR_TYPE = $(shell python3 -m platform) export GHDL_VERSION = $(shell ghdl -v 2>&1 | head -n 1) export BUILD_STRING = $(PROJECT): $(GHDL_VERSION), $(BUILD_SYS_NAME) ($(BUILD_SVR_TYPE)), Built $(BUILD_DATE) by $(BUILD_USER) diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd index 42602b5c9e..bcc5291302 100644 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd @@ -55,6 +55,11 @@ entity Pgp2bAxi is statusWord : out slv(63 downto 0); statusSend : out sl; + -- Debug Interface (axilClk domain) + txDiffCtrl : out slv(4 downto 0); + txPreCursor : out slv(4 downto 0); + txPostCursor : out slv(4 downto 0); + -- AXI-Lite Register Interface (axilClk domain) axilClk : in sl; axilRst : in sl; @@ -90,6 +95,9 @@ architecture structure of Pgp2bAxi is signal syncFlowCntlDis : sl; type RegType is record + txDiffCtrl : slv(4 downto 0); + txPreCursor : slv(4 downto 0); + txPostCursor : slv(4 downto 0); flush : sl; resetTx : sl; resetRx : sl; @@ -105,6 +113,9 @@ architecture structure of Pgp2bAxi is end record RegType; constant REG_INIT_C : RegType := ( + txDiffCtrl => "11111", + txPreCursor => "00111", + txPostCursor => "01111", flush => '0', resetTx => '0', resetRx => '0', @@ -566,6 +577,12 @@ begin v.autoStatus := axilWriteMaster.wdata(0); when X"18" => v.flowCntlDis := ite(WRITE_EN_G, axilWriteMaster.wdata(0), '0'); + when X"1C" => + if WRITE_EN_G then + v.txDiffCtrl := axilWriteMaster.wdata(4 downto 0); + v.txPreCursor := axilWriteMaster.wdata(9 downto 5); + v.txPostCursor := axilWriteMaster.wdata(14 downto 10); + end if; when others => null; end case; @@ -595,6 +612,10 @@ begin v.axilReadSlave.rdata(0) := r.autoStatus; when X"18" => v.axilReadSlave.rdata(0) := r.flowCntlDis; + when X"1C" => + v.axilReadSlave.rdata(4 downto 0) := r.txDiffCtrl; + v.axilReadSlave.rdata(9 downto 5) := r.txPreCursor; + v.axilReadSlave.rdata(14 downto 10) := r.txPostCursor; when X"20" => v.axilReadSlave.rdata(0) := rxStatusSync.phyRxReady; v.axilReadSlave.rdata(1) := txStatusSync.phyTxReady; @@ -671,6 +692,9 @@ begin -- Outputs axilReadSlave <= r.axilReadSlave; axilWriteSlave <= r.axilWriteSlave; + txDiffCtrl <= r.txDiffCtrl; + txPreCursor <= r.txPreCursor; + txPostCursor <= r.txPostCursor; end process; diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd index a7dee767d5..2eb515de10 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd @@ -56,6 +56,7 @@ architecture mapping of Pgp4TxLiteWrapper is signal pgpTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal pgpTxSlave : AxiStreamSlaveType; + signal rstL : sl; begin @@ -87,13 +88,15 @@ begin locRxFifoCtrl(0)=> AXI_STREAM_CTRL_UNUSED_C, locRxLinkReady => '1', remRxFifoCtrl(0)=> AXI_STREAM_CTRL_UNUSED_C, - remRxLinkReady => '1', + remRxLinkReady => '1', -- PHY interface - phyTxActive => '1', + phyTxActive => rstL, phyTxReady => phyTxReady, phyTxValid => phyTxValid, phyTxStart => open, phyTxData => phyTxData(63 downto 0), phyTxHeader => phyTxData(65 downto 64)); + rstL <= not(rst); + end architecture mapping; diff --git a/python/surf/devices/ti/_Lmx2594.py b/python/surf/devices/ti/_Lmx2594.py index 6ad9bd6a11..212f4a1b17 100644 --- a/python/surf/devices/ti/_Lmx2594.py +++ b/python/surf/devices/ti/_Lmx2594.py @@ -227,18 +227,19 @@ def addLinkVariable(name, description, offset, bitSize, mode, bitOffset=0, pollI @self.command(description='Load the CodeLoader .HEX file',value='',) def LoadCodeLoaderHexFile(arg): + self.DataBlock.set(value=0x2410,index=0, write=True) # MUXOUT_LD_SEL=readback + ################################################################## # For the most reliable programming, TI recommends this procedure: ################################################################## # 1. Apply power to device. - reg = self.DataBlock.get(index=0, read=True) # 2. Program RESET = 1 to reset registers. - self.DataBlock.set(value=(reg|0x2), index=0, write=True) + self.DataBlock.set(value=0x2412, index=0, write=True) # 3. Program RESET = 0 to remove reset. - self.DataBlock.set(value=(reg&0xFFFD), index=0, write=True) + self.DataBlock.set(value=0x2410, index=0, write=True) # 4. Program registers as shown in the register map in REVERSE order from highest to lowest. with open(arg, 'r') as ifd: @@ -250,10 +251,9 @@ def LoadCodeLoaderHexFile(arg): # print( f'addr={addr}, data={hex(data)}' ) self.DataBlock.set(value=data, index=addr, write=True) - self.DataBlock.set(value=data, index=addr, write=True) - # 5. Wait 10 ms. time.sleep(0.1) # 6. Program register R0 one additional time with FCAL_EN = 1 to ensure that the VCO calibration runs from a stable state. - self.DataBlock.set(value=(data|0x8), index=0, write=True) + self.DataBlock.set(value=data&0xFFFB, index=addr, write=True) + time.sleep(0.1) diff --git a/python/surf/protocols/pgp/_Pgp2bAxi.py b/python/surf/protocols/pgp/_Pgp2bAxi.py index cbfda5f6b0..34a53ecb7f 100644 --- a/python/surf/protocols/pgp/_Pgp2bAxi.py +++ b/python/surf/protocols/pgp/_Pgp2bAxi.py @@ -73,6 +73,30 @@ def __init__(self, base = pr.Bool, )) + self.add(pr.RemoteVariable( + name = "TxDiffCtrl", + offset = 0x1C, + bitSize = 5, + bitOffset = 0, + mode = "RW", + )) + + self.add(pr.RemoteVariable( + name = "TxPreCursor", + offset = 0x1C, + bitSize = 5, + bitOffset = 5, + mode = "RW", + )) + + self.add(pr.RemoteVariable( + name = "TxPostCursor", + offset = 0x1C, + bitSize = 5, + bitOffset = 10, + mode = "RW", + )) + self.add(pr.RemoteVariable( name = "RxPhyReady", offset = 0x20, diff --git a/python/surf/xilinx/_RfDataConverter.py b/python/surf/xilinx/_RfDataConverter.py index f70e61d4fb..b5186261c3 100644 --- a/python/surf/xilinx/_RfDataConverter.py +++ b/python/surf/xilinx/_RfDataConverter.py @@ -125,6 +125,42 @@ def __init__( expand = False, )) + for i in range(2): + self.add(pr.RemoteVariable( + name = f'MtsFifoCtrl[{i}]', + description = 'index[0] is MtsFifoCtrlADC, index[1] is MtsFifoCtrlDAC', + offset = 0x0010+4*i, + bitSize = 2, + bitOffset = 0, + mode = 'RW', + hidden = True, + )) + + self.add(pr.RemoteVariable( + name = 'MtsSysRefEnable', + offset = 0x6000+0x1C00+(0x24<<2), # XRFDC_DAC_TILE_DRP_ADDR(0) + XRFDC_HSCOM_ADDR offsets + XRFDC_MTS_SRCAP_T1 + bitSize = 1, + bitOffset = 10, # XRFDC_MTS_SRCAP_EN_TRX_M=0x0400 + mode = 'RW', + hidden = True, + )) + + def MtsAdcSync(self): + # Disable the FIFOs + self.MtsFifoCtrl[0].set(0x2) + # Enable SysRef Rx + self.MtsSysRefEnable.set(1) + # Disable the FIFOs + self.MtsFifoCtrl[0].set(0x3) + + def MtsDacSync(self): + # Disable the FIFOs + self.MtsFifoCtrl[1].set(0x2) + # Enable SysRef Rx + self.MtsSysRefEnable.set(1) + # Disable the FIFOs + self.MtsFifoCtrl[1].set(0x3) + def Init(self, dynamicNco=False): # Useful pointers diff --git a/python/surf/xilinx/_RfTile.py b/python/surf/xilinx/_RfTile.py index fed32f9872..cd16bdfef7 100644 --- a/python/surf/xilinx/_RfTile.py +++ b/python/surf/xilinx/_RfTile.py @@ -59,7 +59,7 @@ def __init__( name = 'RestartStateEnd', description = 'End state for power-on sequence', offset = 0x0008, - bitSize = 8, + bitSize = 4, bitOffset = 0, mode = 'RW', enum = powerOnSequenceSteps, @@ -69,7 +69,7 @@ def __init__( name = 'RestartStateStart', description = 'Start state for power-on sequence', offset = 0x0008, - bitSize = 8, + bitSize = 4, bitOffset = 8, mode = 'RW', enum = powerOnSequenceSteps, @@ -79,7 +79,7 @@ def __init__( name = 'CurrentState', description = 'Current state register', offset = 0x000C, - bitSize = 8, + bitSize = 4, bitOffset = 0, mode = 'RO', pollInterval = 1, diff --git a/python/surf/xilinx/_Xadc.py b/python/surf/xilinx/_Xadc.py index eebc5cd4fd..a53c99cefd 100644 --- a/python/surf/xilinx/_Xadc.py +++ b/python/surf/xilinx/_Xadc.py @@ -22,12 +22,17 @@ def __init__(self, description = "AXI-Lite XADC for Xilinx 7 Series (Refer to PG091 & PG019)", auxChannels = 0, zynq = False, + simpleViewList = ["Temperature", "VccInt", "VccAux", "VccBram"], + pollInterval = 5, **kwargs): super().__init__(description=description, **kwargs) if isinstance(auxChannels, int): auxChannels = list(range(auxChannels)) + self.simpleViewList = simpleViewList + self.simpleViewList.append('enable') + def addPair(name, offset, bitSize, units, bitOffset, description, function, pollInterval=0): self.add(pr.RemoteVariable( name = ("Raw"+name), @@ -56,7 +61,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "degC", function = self.convTemp, - pollInterval = 5, + pollInterval = pollInterval, description = """ The result of the on-chip temperature sensor measurement is stored in this location. The data is MSB justified in the @@ -116,7 +121,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = """ The result of the on-chip VccInt supply monitor measurement is stored at this location. The data is MSB justified in the @@ -164,7 +169,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = """ The result of the on-chip VccAux supply monitor measurement is stored at this location. The data is MSB justified in the @@ -214,7 +219,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 4, units = "V", function = self.convCoreVoltage, - pollInterval = 5, + pollInterval = pollInterval, description = """ The result of the on-chip VccBram supply monitor measurement is stored at this location. The data is MSB justified in the @@ -331,6 +336,8 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll variable=self.AuxRaw[ch], linkedGet=self.convAuxVoltage)) + self.simpleViewList.append(f'Aux[{ch}]') + if (zynq): addPair( name = 'VccpInt', @@ -610,5 +617,5 @@ def simpleView(self): # Hide all the variable self.hideVariables(hidden=True) # Then unhide the most interesting ones - vars = ["enable", "Temperature", "VccInt", "VccAux", "VccBram"] + vars = self.simpleViewList self.hideVariables(hidden=False, variables=vars) diff --git a/ruckus.tcl b/ruckus.tcl index 6238316e6b..caa5da374f 100644 --- a/ruckus.tcl +++ b/ruckus.tcl @@ -3,7 +3,7 @@ source $::env(RUCKUS_PROC_TCL) # Check for submodule tagging if { [info exists ::env(OVERRIDE_SUBMODULE_LOCKS)] != 1 || $::env(OVERRIDE_SUBMODULE_LOCKS) == 0 } { - if { [SubmoduleCheck {ruckus} {4.8.4} ] < 0 } {exit -1} + if { [SubmoduleCheck {ruckus} {4.9.0} ] < 0 } {exit -1} } else { puts "\n\n*********************************************************" puts "OVERRIDE_SUBMODULE_LOCKS != 0" diff --git a/xilinx/general/microblaze/ruckus.tcl b/xilinx/general/microblaze/ruckus.tcl index e9b79adb2e..65e47b3310 100644 --- a/xilinx/general/microblaze/ruckus.tcl +++ b/xilinx/general/microblaze/ruckus.tcl @@ -19,7 +19,8 @@ if { [info exists ::env(VITIS_SRC_PATH)] != 1 } { loadSource -lib surf -path "$::DIR_PATH/generate/MicroblazeBasicCoreWrapper.vhd" # Load the .bd file - if { $::env(VIVADO_VERSION) == 2023.1 || + if { $::env(VIVADO_VERSION) == 2023.2 || + $::env(VIVADO_VERSION) == 2023.1 || $::env(VIVADO_VERSION) == 2022.2 } { puts "\nVivado v$::env(VIVADO_VERSION) not supported for general/microblaze\n" exit -1 diff --git a/yaml/Pgp2bAxi.yaml b/yaml/Pgp2bAxi.yaml index 3d6cc02f13..4abc6f9180 100644 --- a/yaml/Pgp2bAxi.yaml +++ b/yaml/Pgp2bAxi.yaml @@ -97,6 +97,33 @@ Pgp2bAxi: &Pgp2bAxi mode: RW description: "Auto Status Send Enable (PPI)" ######################################################### + TxDiffCtrl: + at: + offset: 0x1C + class: IntField + sizeBits: 5 + lsBit: 0 + mode: RW + description: "GT Tx Diff Voltage Control" + ######################################################### + TxPreCursor: + at: + offset: 0x1C + class: IntField + sizeBits: 5 + lsBit: 5 + mode: RW + description: "GT Tx Pre Cursor Control" + ######################################################### + TxPostCursor: + at: + offset: 0x1D + class: IntField + sizeBits: 5 + lsBit: 2 + mode: RW + description: "GT Tx Pre Cursor Control" + ######################################################### RxPhyReady: at: offset: 0x20 diff --git a/yaml/SsiPrbsRx.yaml b/yaml/SsiPrbsRx.yaml index b0d2b46c66..9cadc9af86 100644 --- a/yaml/SsiPrbsRx.yaml +++ b/yaml/SsiPrbsRx.yaml @@ -57,13 +57,13 @@ SsiPrbsRx: &SsiPrbsRx mode: RO description: Number of word errors ######################################################### - BitStrbErrCnt: - at: - offset: 0x14 - class: IntField - name: BitStrbErrCnt - mode: RO - description: Number of bit errors +# BitStrbErrCnt: +# at: +# offset: 0x14 +# class: IntField +# name: BitStrbErrCnt +# mode: RO +# description: Number of bit errors ######################################################### RxFifoOverflowCnt: at: @@ -107,7 +107,7 @@ SsiPrbsRx: &SsiPrbsRx ######################################################### Status: at: - offset: 0x1C0 + offset: 0x70 class: IntField name: Status mode: RO @@ -115,7 +115,7 @@ SsiPrbsRx: &SsiPrbsRx ######################################################### PacketLength: at: - offset: 0x1C4 + offset: 0x74 class: IntField name: PacketLength mode: RO @@ -123,23 +123,23 @@ SsiPrbsRx: &SsiPrbsRx ######################################################### PacketRate: at: - offset: 0x1C8 + offset: 0x78 class: IntField name: PacketRate mode: RO description: '' ######################################################### - BitErrCnt: - at: - offset: 0x1CC - class: IntField - name: BitErrCnt - mode: RO - description: '' +# BitErrCnt: +# at: +# offset: 0x1CC +# class: IntField +# name: BitErrCnt +# mode: RO +# description: '' ######################################################### WordErrCnt: at: - offset: 0x1D0 + offset: 0x80 class: IntField name: WordErrCnt mode: RO @@ -147,7 +147,7 @@ SsiPrbsRx: &SsiPrbsRx ######################################################### RolloverEnable: at: - offset: 0x3C0 + offset: 0xF0 class: IntField name: RolloverEnable mode: RW @@ -155,7 +155,7 @@ SsiPrbsRx: &SsiPrbsRx ######################################################### CntRst: at: - offset: 0x3FC + offset: 0xFC class: IntField name: CntRst sizeBits: 1