diff --git a/slothy/targets/arm_v7m/arch_v7m.py b/slothy/targets/arm_v7m/arch_v7m.py
index 1de96011..7b3a9bd1 100644
--- a/slothy/targets/arm_v7m/arch_v7m.py
+++ b/slothy/targets/arm_v7m/arch_v7m.py
@@ -1167,6 +1167,20 @@ class movt_imm(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,inval
     pattern = "movt <Rd>, <imm>"
     in_outs = ["Rd"]
 
+class mov(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "mov <Rd>,<Ra>"
+    inputs = ["Ra"]
+    outputs = ["Rd"]
+
+class mov_imm(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "mov <Rd>,<imm>"
+    outputs = ["Rd"]
+
+class movs_imm(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "movs <Rd>,<imm>"
+    outputs = ["Rd"]
+    modifiesFlags=True
+
 # Addition
 class add(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
     pattern = "add<width> <Rd>, <Ra>, <Rb>"
@@ -1198,6 +1212,18 @@ class adds(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-n
     outputs = ["Rd"]
     modifiesFlags=True
 
+class adds_short(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "adds<width> <Rd>,<Ra>"
+    inputs = ["Ra"]
+    in_outs = ["Rd"]
+    modifiesFlags=True
+
+class adds_imm(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "adds<width> <Rd>,<Ra>,<imm>"
+    inputs = ["Ra"]
+    outputs = ["Rd"]
+    modifiesFlags=True
+
 class uadd16(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
     pattern = "uadd16<width> <Rd>, <Ra>, <Rb>"
     inputs = ["Ra","Rb"]
@@ -1208,6 +1234,32 @@ class sadd16(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid
     inputs = ["Ra","Rb"]
     outputs = ["Rd"]
 
+class adc(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "adc<width> <Rd>,<Ra>,<Rb>"
+    inputs = ["Ra", "Rb"]
+    outputs = ["Rd"]
+    dependsOnFlags=True
+
+class adcs(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "adcs<width> <Rd>,<Ra>,<Rb>"
+    inputs = ["Ra", "Rb"]
+    outputs = ["Rd"]
+    dependsOnFlags=True
+    modifiesFlags=True
+
+class adcs_short(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "adcs<width> <Rd>,<Ra>"
+    inputs = ["Ra"]
+    in_outs = ["Rd"]
+    dependsOnFlags=True
+    modifiesFlags=True
+
+class adcs_imm_short(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "adcs<width> <Rd>,<imm>"
+    in_outs = ["Rd"]
+    dependsOnFlags=True
+    modifiesFlags=True
+
 # Subtraction
 class sub(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
     pattern = "sub<width> <Rd>, <Ra>, <Rb>"
@@ -1234,11 +1286,30 @@ class subs_imm(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,inval
     outputs = ["Rd"]
     modifiesFlags = True
 
+class subs_short(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "subs<width> <Rd>,<Ra>"
+    inputs = ["Ra"]
+    in_outs = ["Rd"]
+    modifiesFlags = True
+
 class subs_imm_short(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
     pattern = "subs<width> <Ra>, <imm>"
     in_outs = ["Ra"]
     modifiesFlags = True
 
+class sbc_short(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "sbc<width> <Rd>,<Ra>"
+    inputs = ["Ra"]
+    in_outs = ["Rd"]
+    dependsOnFlags=True
+
+class sbcs_short(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "sbcs<width> <Rd>,<Ra>"
+    inputs = ["Ra"]
+    in_outs = ["Rd"]
+    modifiesFlags = True
+    dependsOnFlags=True
+
 class usub16(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
     pattern = "usub16<width> <Rd>, <Ra>, <Rb>"
     inputs = ["Ra","Rb"]
@@ -1354,6 +1425,16 @@ class smuadx(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-
 
 # Logical
 
+class umaal(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "umaal<width> <Ra>,<Rb>,<Rc>,<Rd>"
+    inputs = ["Rc","Rd"]
+    in_outs = ["Ra", "Rb"]
+
+class umull(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "umull<width> <Ra>,<Rb>,<Rc>,<Rd>"
+    inputs = ["Rc","Rd"]
+    outputs = ["Ra", "Rb"]
+
 class neg_short(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
     pattern = "neg<width> <Rd>, <Ra>"
     inputs = ["Ra"]
@@ -1368,6 +1449,11 @@ class log_and_shifted(Armv7mShiftedLogical): # pylint: disable=missing-docstring
     inputs = ["Ra", "Rb"]
     outputs = ["Rd"]
 
+class log_and_imm(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "and<width> <Rd>,<Ra>,<imm>"
+    inputs = ["Ra"]
+    outputs = ["Rd"]
+
 class log_or(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
     pattern = "orr<width> <Rd>, <Ra>, <Rb>"
     inputs = ["Ra", "Rb"]
@@ -1414,6 +1500,11 @@ class bic(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
     inputs = ["Ra", "Rb"]
     outputs = ["Rd"]
 
+class bic_imm(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "bic<width> <Rd>,<Ra>,<imm>"
+    inputs = ["Ra"]
+    outputs = ["Rd"]
+
 class bics(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
     pattern = "bics<width> <Rd>, <Ra>, <Rb>"
     inputs = ["Ra", "Rb"]
@@ -1486,7 +1577,6 @@ def make(cls, src):
         obj.increment = None
         obj.pre_index = 0
         obj.addr = obj.args_in[0]
-        obj.args_in_out_different = [(0,0)] # Can't have Rd==Ra
         return obj
 
     def write(self):
@@ -1505,7 +1595,6 @@ def make(cls, src):
         obj.increment = None
         obj.pre_index = obj.immediate
         obj.addr = obj.args_in[0]
-        obj.args_in_out_different = [(0,0)] # Can't have Rd==Ra
         return obj
 
     def write(self):
@@ -1528,7 +1617,6 @@ def make(cls, src):
         obj = Armv7mInstruction.build(cls, src)
         obj.increment = None
         obj.pre_index = obj.immediate
-        obj.args_in_out_different = [(0,0)] # Can't have Rd==Ra
         obj.addr = obj.args_in[0]
         return obj
 
@@ -1545,7 +1633,6 @@ def make(cls, src):
         obj = Armv7mInstruction.build(cls, src)
         obj.increment = None
         obj.pre_index = obj.immediate
-        obj.args_in_out_different = [(0,0)] # Can't have Rd==Ra
         obj.addr = obj.args_in[0]
         return obj
 
@@ -1625,6 +1712,17 @@ def make(cls, src):
         obj.addr = obj.args_in_out[0]
         return obj
 
+class ldrd_with_imm_stack(Ldrd): # pylint: disable=missing-docstring,invalid-name
+    pattern = "ldrd<width> <Rd>,<Ra>,[sp,<imm>]"
+    outputs = ["Rd","Ra"]
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mInstruction.build(cls, src)
+        obj.increment = None
+        obj.pre_index = obj.immediate
+        obj.addr = "sp"
+        return obj
+
 class ldrd_with_postinc(Ldrd): # pylint: disable=missing-docstring,invalid-name
     pattern = "ldrd<width> <Ra>, <Rb>, [<Rc>], <imm>"
     in_outs = [ "Rc" ]
@@ -1828,6 +1926,22 @@ def write(self):
         self.immediate = simplify(self.pre_index)
         return super().write()
 
+class strd_with_imm_stack(Armv7mStoreInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "strd<width> <Rd>,<Ra>,[sp,<imm>]"
+    inputs = ["Rd","Ra"]
+    outputs = []
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mInstruction.build(cls, src)
+        obj.increment = None
+        obj.pre_index = obj.immediate
+        obj.addr = "sp"
+        return obj
+
+    def write(self):
+        self.immediate = simplify(self.pre_index)
+        return super().write()
+
 class str_with_postinc(Armv7mStoreInstruction): # pylint: disable=missing-docstring,invalid-name
     pattern = "str<width> <Rd>, [<Ra>], <imm>"
     inputs = ["Rd"]
@@ -1893,6 +2007,61 @@ class bne(Armv7mBranch): # pylint: disable=missing-docstring,invalid-name
     pattern = "bne<width> <label>"
     dependsOnFlags=True
 
+# TODO: model depenency through stack correctly
+class push(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "push<width> <reg_list>"
+    in_outs = []
+    outputs = []
+
+    def write(self):
+        regs = ",".join(self.args_in)
+        self.reg_list = f"{{{regs}}}"
+        return super().write()
+
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mLoadInstruction.build(cls, src)
+        reg_list_type, reg_list = Armv7mInstruction._expand_reg_list(obj.reg_list)
+
+        obj.addr = "sp"
+        obj.args_in = reg_list
+        obj.num_in = len(obj.args_in)
+        obj.arg_types_in = [RegisterType.GPR] * obj.num_in
+        obj.increment = obj.num_in * 4
+
+        available_regs = RegisterType.list_registers(RegisterType.GPR)
+        obj.args_in_combinations =  [ (list(range(0, obj.num_in)), [list(a) for a in itertools.combin
+ations(available_regs, obj.num_in)])]
+        obj.args_in_restrictions = [ None for _ in range(obj.num_in)    ]
+        return obj
+
+class pop(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "pop<width> <reg_list>"
+    in_outs = []
+    outputs = []
+
+    def write(self):
+        regs = ",".join(self.args_out)
+        self.reg_list = f"{{{regs}}}"
+        return super().write()
+
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mLoadInstruction.build(cls, src)
+        reg_list_type, reg_list = Armv7mInstruction._expand_reg_list(obj.reg_list)
+
+        obj.addr = "sp"
+        obj.args_out = reg_list
+        obj.num_out = len(obj.args_out)
+        obj.arg_types_out = [RegisterType.GPR] * obj.num_out
+        obj.increment = obj.num_out * 4
+
+        available_regs = RegisterType.list_registers(RegisterType.GPR)
+        obj.args_out_combinations =  [ (list(range(0, obj.num_out)), [list(a) for a in itertools.combinations(available_regs, obj.num_out)])]
+        obj.args_out_restrictions = [ None for _ in range(obj.num_out)    ]
+        return obj
+
+
 class Spill:
     def spill(reg, loc, spill_to_vreg=None):
         """Generates the instruction text for a spill to either
diff --git a/slothy/targets/arm_v7m/cortex_m7.py b/slothy/targets/arm_v7m/cortex_m7.py
index 3fb89716..baa21b7e 100644
--- a/slothy/targets/arm_v7m/cortex_m7.py
+++ b/slothy/targets/arm_v7m/cortex_m7.py
@@ -66,6 +66,12 @@ def add_mac_slot_constraint(slothy):
         [mul, mul_short, smull, smlal, mla, mls, smulwb, smulwt, smultb, smultt,
      smulbb, smlabt, smlabb, smlatt, smlatb, smlad, smladx, smuad, smuadx, smmulr], [1])
 
+# TODO: this seems incorrect
+def add_slot_constraints(slothy):
+   slothy.restrict_slots_for_instructions_by_class(
+        [str_with_imm, str_with_imm_stack, str_with_postinc, strh_with_imm,
+    strh_with_postinc, stm_interval_inc_writeback, str_no_off, str], [1])
+
 def add_st_hazard(slothy):
     def is_st_ld_pair(inst_a, inst_b):
         return (isinstance(inst_a.inst, ldr_with_imm) or isinstance(inst_a.inst, ldr_with_imm_stack)) \
@@ -121,12 +127,14 @@ def get_min_max_objective(slothy):
         ): ExecutionUnit.LOAD(),
     (
         Ldrd,
+        ldrd_with_imm_stack,
         ldm_interval,
         ldm_interval_inc_writeback,
         vldm_interval_inc_writeback): [ExecutionUnit.LOAD()],
     (
         str_with_imm,
         str_with_imm_stack,
+        strd_with_imm_stack,
         str_with_postinc,
         str_no_off,
         strh_with_imm,
@@ -134,24 +142,42 @@ def get_min_max_objective(slothy):
         stm_interval_inc_writeback
     ): [[ExecutionUnit.STORE, ExecutionUnit.MAC]],
     (
+        mov,
+        mov_imm,
+        movs_imm,
         movw_imm,
         movt_imm,
+        adc,
+        adcs,
+        adcs_short,
+        adcs_imm_short,
         adds,
+        adds_imm,
+        adds_short,
         add,
         add_short,
         add_imm,
         add_imm_short,
-        sub, subs_imm, subs_imm_short, sub_imm_short,
+        sbc_short,
+        sbcs_short,
+        sub, subs_imm, subs_short,subs_imm_short, sub_imm_short,
+        sub_short,
         neg_short,
         log_and,
+        # To check:didn't have log_and_shifted,is't execute?
+        log_and_imm,
         log_or,
         eor, eor_short, eors, eors_short,
         bic, bics,
+        bic_imm,
         cmp, cmp_imm,
+        # To do: To do: Not sure where to put the 'pop' and 'push' classes.the book?
+        pop,push,
+
         bne
     ): ExecutionUnit.ALU(),
     (ror, ror_short, rors_short, lsl, asr, asrs): [[ExecutionUnit.ALU0], [ExecutionUnit.ALU1]],
-    (mul, mul_short, smull, smlal, mla, mls, smulwb, smulwt, smultb, smultt,
+    (mul, mul_short, smull, umaal, umull, smlal, mla, mls, smulwb, smulwt, smultb, smultt,
      smulbb, smlabt, smlabb, smlatt, smlatb, smlad, smladx, smuad, smuadx, smmulr): [ExecutionUnit.MAC],
     (vmov_gpr, vmov_gpr2, vmov_gpr2_dual): [ExecutionUnit.FPU],
     (uadd16, sadd16, usub16, ssub16): list(map(list, product(ExecutionUnit.ALU(), [ExecutionUnit.SIMD]))),
@@ -167,6 +193,7 @@ def get_min_max_objective(slothy):
         ldr_with_inc_writeback,
         ldr_with_postinc,
         Ldrd,
+        ldrd_with_imm_stack,
         ldrb_with_imm,
         ldrh_with_imm,
         ldrh_with_postinc,
@@ -174,28 +201,46 @@ def get_min_max_objective(slothy):
         vldr_with_imm, vldr_with_postinc,  # TODO: double-check
         # actually not, just placeholder
         ldm_interval, ldm_interval_inc_writeback, vldm_interval_inc_writeback,
+        mov,
+        mov_imm,
+        movs_imm,
         movw_imm,
         movt_imm,
+        adc,
+        adcs,
+        adcs_short,
+        adcs_imm_short,
         adds,
+        adds_imm,
+        adds_short,
+        add_short,
         add,
         add_short,
         add_imm,
         add_imm_short,
         add_shifted,
+        sbc_short,
+        sbcs_short,
         sub_shifted,
+        sub_short,
         sub_imm_short,
+        subs_short,
         subs_imm,
         subs_imm_short,
         uadd16, sadd16, usub16, ssub16,
         mul, mul_short,
         smull,
+        umaal,
+        umull,
         smlal,
         mla, mls, smulwb, smulwt, smultb, smultt, smulbb, smlabt, smlabb, smlatt, smlatb, smlad, smladx, smuad, smuadx, smmulr,
         neg_short,
         log_and, log_and_shifted,
+        log_and_imm,
         log_or, log_or_shifted,
         eor, eor_short, eors, eors_short,
         eor_shifted,
+        bic_imm,
         bic, bics,
         bic_shifted,
         ror, ror_short, rors_short, lsl, asr, asrs,
@@ -205,10 +250,12 @@ def get_min_max_objective(slothy):
         pkhbt, pkhtb, pkhbt_shifted, ubfx_imm,
         str_with_imm,
         str_with_imm_stack,
+        strd_with_imm_stack,
         str_with_postinc,
         str_no_off,
         strh_with_imm,
         strh_with_postinc,
+        pop,push,
         bne
 
     ): 1,
@@ -219,23 +266,40 @@ def get_min_max_objective(slothy):
 
 default_latencies = {
     (
+        mov,
+        mov_imm,
+        movs_imm,
         movw_imm,
         movt_imm,
+        adc,
+        adcs,
+        adcs_short,
+        adcs_imm_short,
         adds,
+        adds_imm,
+        adds_short,
+        add_short,
         add,
         add_short,
         add_imm,
         add_imm_short,
         add_shifted,
+        sbc_short,
+        sbcs_short,
         sub_shifted,
+        sub_short,
         sub_imm_short,
+        sub_short,
+        subs_short,
         subs_imm,
         subs_imm_short,
         uadd16, sadd16, usub16, ssub16,
         neg_short,
         log_and, log_and_shifted,
+        log_and_imm,
         log_or, log_or_shifted,
         eor, eor_short, eors, eors_short,
+        bic_imm,
         bic, bics,
         bic_shifted,
         ror, ror_short, rors_short, lsl, asr, asrs,
@@ -246,16 +310,20 @@ def get_min_max_objective(slothy):
         ldm_interval, ldm_interval_inc_writeback, vldm_interval_inc_writeback,
         str_with_imm,
         str_with_imm_stack,
+        strd_with_imm_stack,
         str_with_postinc,
         str_no_off,
         strh_with_imm,
         strh_with_postinc,
+        pop,push,
         bne
     ): 1,
     (
         mul, mul_short,
         smull,
         smlal,
+        umaal,
+        umull,
         mla, mls, smulwb, smulwt, smultb, smultt, smulbb, smlabt, smlabb, smlatt, smlatb, smlad, smladx, smuad, smuadx, smmulr,
         # TODO: Verify load latency
         stm_interval_inc_writeback,  # actually not, just placeholder
@@ -271,7 +339,7 @@ def get_min_max_objective(slothy):
         ldrb_with_postinc,
         eor_shifted
     ): 2,
-    (Ldrd): 3,
+    (Ldrd,ldrd_with_imm_stack): 3,
     (vmov_gpr2, vmov_gpr2_dual): 3,
     (vmov_gpr): 1
 }
@@ -298,7 +366,8 @@ def get_latency(src, out_idx, dst):
                 latency = latency - 1
 
     # Multiply accumulate chain latency is 1
-    if instclass_src in [smlal] and instclass_dst in [smlal] and \
+    # TODO: verify this for umaal
+    if instclass_src in [smlal] and instclass_dst in [smlal, umaal] and \
             src.args_in_out[0] == dst.args_in_out[0] and \
             src.args_in_out[1] == dst.args_in_out[1]:
         return 1
@@ -365,4 +434,4 @@ def get_inverse_throughput(src):
     if find_class(src) in [ldm_interval, ldm_interval_inc_writeback, stm_interval_inc_writeback, vldm_interval_inc_writeback]:
         itp = src.num_out
 
-    return itp
+    return itp
\ No newline at end of file