Add caching for host buffers that are bigger than RAM.

[tugrul512bit]

Backing store: SSD with 3GB/s bandwidth, serialized access from all threads.

L2: combined VRAMs of devices, with PCIE bandwidth (so quad titans can make good cache layer) but high latency, LRU.

L1: RAM that has 60+ GB/s for DDR5 (even more if data fits into CPU cache), direct-mapped.

This works only for dynamic-load balancing with static chunk size and atomic signaling from kernel on only RAM-sharing devices or normal devices with periodic buffer copies to express memory region request within kernel and only for opencl 2.x.