How to bind a proprietary SRAM compiler

[Z-KN]

I want to invoke a memory compiler with the hammer. I have read https://chipyard.readthedocs.io/en/stable/Tools/Barstools.html#mapping-technology-srams-macrocompiler but it is vague to me. I noticed the --use-compiler option; my proprietary memory compiler is just a .pl script, how could I bind/invoke this Perl script with hammer?

I also noticed some json files such as https://github.com/ucb-bar/hammer/blob/8fd1486499b875d56f09b060f03a62775f0a6aa7/src/hammer-vlsi/technology/nangate45/sram-cache.json . Do I also need to provide this either? How is it related to the SRAM compiler program?

[harrisonliew]

Hi,

I gave a pretty detailed explanation of how to write the sram-compiler.json file and __init__.py file to call the Perl script in this Chipyard Google Group conversation from a while back: https://groups.google.com/g/chipyard/c/-T6-mvQZmOM, specifically the 2nd message. You will need to pay attention to the Using Hammer (advanced) section and implement the SRAMGroup format in the sram-compiler.json file.

Please see if you can understand this and feel free to ask any up follow-up questions.

[Z-KN]

This is a very nice explanation! I generally know what files should be provided. Yet from a high-level view, how could hammer handle the physical flow with respect to SRAM?

I found in my generated-src directories, there are many ram_2x<yy>.sv files, data_array_<yy>.sv, as well as cc_bank_<yy>.sv files, in which ram in Verilog form is transformed from SyncReadMem in Chisel form. E.g., // @[generators/rocket-chip/src/main/scala/util/DescribedSRAM.scala:17:26]. So does it mean, hammer will automatically detect those .sv files that have components transformed from SyncReadMem , and invoke the foundry memory compiler to generate SRAM layouts, and use those layouts in later stages such as P&R?

And is the generation of generated-src aware of the SRAM compiler? Meaning, will the front-end generate .sv files in generated-src differently if the defaults.yml specifies a foundry compiler? In other words, "the cost function setting of MacroCompiler allows the user to tune the mapping to their preference", does it mean users can get different .sv files when they tune differently in the defaults.yml file?

[harrisonliew]

Ah. I think clarification on the distinction between the barstools MacroCompiler and Hammer's SRAMGenerator is necessary. It is a 2-step flow.

Step 1: MacroCompiler takes the memories required by Chisel (SyncReadMem instances in those .sv files you mention) and reads in a SRAMMacro or SRAMGroup description of available memories (the json files provided in the plugin) in order to replace them with instances of memories provided in the technology (transforms the .sv files and adds a <config>.top.mems.v file). It also emits a json file in Hammer IR format (<config>.mems.hammer.json) that is used in the next step. Chisel elaboration (generating generated-src) is not SRAM compiler aware, hence it requires the additional MacroCompiler step.

Step 2: Hammer's SRAMGenerator is subclassed in the tech plugin's __init__.py file (defaults.yml is not relevant here except to select vlsi.core.sram_generator_tool) and run with the sram_generator action. This takes the list of required memories from the <config>.mems.hammer.json file and runs the Perl foundry compiler for only the required memories, then packages the output collateral into a list of vlsi.inputs.extra_libraries. You can proceed with synthesis/simulation after this point.

TL;DR: MacroCompiler (a FIRRTL pass) is separate from Hammer. MacroCompiler only needs a JSON file describing the memories and outputs Hammer IR. Then, Hammer takes this to run your foundry compiler.

P.S. We need to replace MacroCompiler because we would like to complete the migration of FIRRTL to CIRCT compiler in Chipyard. It would become a Chisel library instead, thus making the distinction even clearer.

[Z-KN]

Thanks for the clarification! I may get it:

1. Chisel elaboration generates generate-src, which contains two files called <config>.tops.mems.conf and <config>.tops.mems.v (the latter appears in my sims already).
2. Then, the MacroCompiler also generates <config>.mems.hammer.json based on <config>.tops.mems.conf. The <config>.mems.hammer.json is all the memory to be compiled as SRAM. The following is RocketConfig.mems.hammer.json without giving sram-compiler.json:

[
{"type":"sram","name":"SRAM1RW1024x17","width":17,"depth":"1024","mux":1,"mask":false,"ports":[{"address port name":"A","address port polarity":"active high","clock port name":"CE","clock port polarity":"positive edge","write enable port name":"WEB","write enable port polarity":"active low","read enable port name":"OEB","read enable port polarity":"active low","chip enable port name":"CSB","chip enable port polarity":"active low","output port name":"O","output port polarity":"active high","input port name":"I","input port polarity":"active high"}],"family":"1RW","vt":"SRAM"}
,
{"type":"sram","name":"SRAM1RW1024x64","width":64,"depth":"1024","mux":1,"mask":false,"ports":[{"address port name":"A","address port polarity":"active high","clock port name":"CE","clock port polarity":"positive edge","write enable port name":"WEB","write enable port polarity":"active low","read enable port name":"OEB","read enable port polarity":"active low","chip enable port name":"CSB","chip enable port polarity":"active low","output port name":"O","output port polarity":"active high","input port name":"I","input port polarity":"active high"}],"family":"1RW","vt":"SRAM"}
,
{"type":"sram","name":"SRAM1RW512x8","width":8,"depth":"512","mux":1,"mask":false,"ports":[{"address port name":"A","address port polarity":"active high","clock port name":"CE","clock port polarity":"positive edge","write enable port name":"WEB","write enable port polarity":"active low","read enable port name":"OEB","read enable port polarity":"active low","chip enable port name":"CSB","chip enable port polarity":"active low","output port name":"O","output port polarity":"active high","input port name":"I","input port polarity":"active high"}],"family":"1RW","vt":"SRAM"}
,
{"type":"sram","name":"SRAM1RW64x22","width":22,"depth":"64","mux":1,"mask":false,"ports":[{"address port name":"A","address port polarity":"active high","clock port name":"CE","clock port polarity":"positive edge","write enable port name":"WEB","write enable port polarity":"active low","read enable port name":"OEB","read enable port polarity":"active low","chip enable port name":"CSB","chip enable port polarity":"active low","output port name":"O","output port polarity":"active high","input port name":"I","input port polarity":"active high"}],"family":"1RW","vt":"SRAM"}
,
{"type":"sram","name":"SRAM1RW64x21","width":21,"depth":"64","mux":1,"mask":false,"ports":[{"address port name":"A","address port polarity":"active high","clock port name":"CE","clock port polarity":"positive edge","write enable port name":"WEB","write enable port polarity":"active low","read enable port name":"OEB","read enable port polarity":"active low","chip enable port name":"CSB","chip enable port polarity":"active low","output port name":"O","output port polarity":"active high","input port name":"I","input port polarity":"active high"}],"family":"1RW","vt":"SRAM"}
,
{"type":"sram","name":"SRAM1RW512x32","width":32,"depth":"512","mux":1,"mask":false,"ports":[{"address port name":"A","address port polarity":"active high","clock port name":"CE","clock port polarity":"positive edge","write enable port name":"WEB","write enable port polarity":"active low","read enable port name":"OEB","read enable port polarity":"active low","chip enable port name":"CSB","chip enable port polarity":"active low","output port name":"O","output port polarity":"active high","input port name":"I","input port polarity":"active high"}],"family":"1RW","vt":"SRAM"}
,
{"type":"sram","name":"SRAM1RW4096x8","width":8,"depth":"4096","mux":1,"mask":false,"ports":[{"address port name":"A","address port polarity":"active high","clock port name":"CE","clock port polarity":"positive edge","write enable port name":"WEB","write enable port polarity":"active low","read enable port name":"OEB","read enable port polarity":"active low","chip enable port name":"CSB","chip enable port polarity":"active low","output port name":"O","output port polarity":"active high","input port name":"I","input port polarity":"active high"}],"family":"1RW","vt":"SRAM"}
]

And the port widths are irregular. So we need a sram-compiler.json to match those wanted SRAMs to standard SRAM specifications.
3. Then, the Hammer's sram_generator invokes the Perl foundry compiler based on <config>.mems.hammer.json.

Is that the case? It seems the MacroCompiler also participates in the step 1 (since it is a FIRRTL pass)?

P.S. Many ram_exts do not appear in the <config>.mems.hammer.json. Does that mean MacroCompiler chooses not to map it to SRAM? Such as ram_2x107 ram_ext ( // @[src/main/scala/chisel3/util/Decoupled.scala:274:95] in ram_2x107.sv.

[harrisonliew]

Pretty close. Indeed, MacroCompiler also participates in step 1 and concurrently generates the <config>.top.mems.v and <config>.mems.hammer.json.

You may want to see the log output when MacroCompiler is running to debug that, such as if it has to do with unsupported ports or mask sizes. The <config>.mems.hammer.json only lists the unique mapped memories, so it's possible that there are multiple instances of any given memory.