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[FMV] Remove features predres and ls64. #382
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These cannot be detected by reading the ID_AA64ISAR1_EL1 register since their corresponding bitfields are hidden according to the Linux Kernel docs: https://www.kernel.org/doc/html/latest/arch/arm64/cpu-feature-registers.html Additionally the instructions that these features enable are unusable from user space (Exception Level 0). For SPECRES the Arm Architecture Reference Manual says: In AArch64 state, EL0 access to the System instructions is controlled by: * When HCR_EL2.{E2H, TGE} is not {1, 1}, SCTLR_EL1.EnRCTX. * When HCR_EL2.{E2H, TGE} == {1, 1}, SCTLR_EL2.EnRCTX. For LS64 it says: * SCTLR_EL1.EnALS, bit [56] : When FEAT_LS64 is implemented: When the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, traps execution of an LD64B or ST64B instruction at EL0 to EL1. * SCTLR_EL1.EnAS0, bit [55] : When FEAT_LS64_ACCDATA is implemented: When the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, traps execution of an ST64BV0 instruction at EL0 to EL1. * SCTLR_EL1.EnASR, bit [54] : When FEAT_LS64_V is implemented: When the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, traps execution of an ST64BV instruction at EL0 to EL1.
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These cannot be detected by reading the ID_AA64ISAR1_EL1 register since their corresponding bitfields are hidden. Additionally the instructions that these features enable are unusable from EL0. ACLE: ARM-software/acle#382
DanielKristofKiss
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LGTM
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These cannot be detected by reading the ID_AA64ISAR1_EL1 register since their corresponding bitfields are hidden. Additionally the instructions that these features enable are unusable from EL0. ACLE: ARM-software/acle#382
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These cannot be detected by reading the ID_AA64ISAR1_EL1 register since their corresponding bitfields are hidden. Additionally the instructions that these features enable are unusable from EL0. ACLE: ARM-software/acle#382
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These cannot be detected by reading the ID_AA64ISAR1_EL1 register since their corresponding bitfields are hidden according to the Linux Kernel docs:
https://www.kernel.org/doc/html/latest/arch/arm64/cpu-feature-registers.html
Additionally the instructions that these features enable are unusable from user space (Exception Level 0).
For SPECRES the Arm Architecture Reference Manual says:
In AArch64 state, EL0 access to the System instructions is controlled by:
For LS64 it says:
SCTLR_EL1.EnALS, bit [56] : When FEAT_LS64 is implemented: When the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, traps execution of an LD64B or ST64B instruction at EL0 to EL1.
SCTLR_EL1.EnAS0, bit [55] : When FEAT_LS64_ACCDATA is implemented: When the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, traps execution of an ST64BV0 instruction at EL0 to EL1.
SCTLR_EL1.EnASR, bit [54] : When FEAT_LS64_V is implemented: When the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, traps execution of an ST64BV instruction at EL0 to EL1.
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