FSMEdit
Note: This feature is a work-in-progress. The generated Verilog code is not valid and Mealy machine support is still not finished. Use at your own discretion.
FSMEdit is a finite state machine editor that can compile finite state machines to Verilog.
There are four tabs on the top.
- To create a state, double click anywhere. Double click again to make it the default (reset) state.
- If a state is clicked once, text editing is enabled. In a Moore machine, to define the output,a forward slash (/) is placed after the state's name preceding an assignment statement. The assignment statement will be copied verbatim to Verilog, so multiple assignments are unsupported at this point in time.
- The delete button deletes states. Backspace will alter the state's text.
- Adding a transition involves shift dragging a state to another state.
- Clicking on a transition allows for text editing as well, first the condition for said transition (again, copied verbatim to Verilog- usually, name or ~name will suffice) and if it's a Mealy machine, a forward slash (/) and then an assignment statement, which should also be moved verbatim to Verilog.
There are fields that are needed to assist with the compilation of the finite state machine, which are to be filled according to the project. Inputs and outputs are comma-delimited.
After compilation, FSMEdit generates read-only Verilog code. The "Export to Verilog" can then generate a new Verilog module representative of the generated finite state machine. There may be minor issues with output generations and synchronous resets; fixing those is advised.
A summarized version of the Designer help as written above.
FSMEdit is based off Evan Wallace's Finite State Machine Designer.
Finite State Machine Designer (http://madebyevan.com/fsm/)
License: MIT License (see below)
Copyright (c) 2010 Evan Wallace
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