Load caps become a property of a testbench, not an opamp

AutoCkt/Server/autockt_server/opamps/TwoStageOpAmp.py

@@ -3,7 +3,7 @@
 """
 
 import hdl21 as h
-from hdl21.prefix import FEMTO
+from hdl21.prefix import FEMTO, PICO, MILLI, MICRO
 from autockt_shared import OpAmpInput, OpAmpOutput
 
 from ..typing import as_hdl21_paramclass, Hdl21Paramclass
@@ -18,9 +18,6 @@
 def TwoStageOpAmp(p: Params) -> h.Module:
     """# Two Stage OpAmp"""
 
-    # FIXME: move to testbench(?)
-    cl = h.prefix.Prefixed(number=1e-11)
-
     # Multiplier functions of the parametric devices
     nbias = lambda x: nmos(m=p.nbias * x)
     ninp = lambda x: nmos(m=p.ninp * x)
@@ -48,15 +45,10 @@ class TwoStageOpAmp:
         # mpld = h.Pair(pmoses(x=p.alpha))(d=out1, g=outn, s=VDD, b=VDD)
         mpld = h.Pair(pmoses(x=p.alpha))(d=out1, g=out1.n, s=VDD, b=VDD)
 
-        # FIXME: hacking out the output stage for the time being
-
         # Output Stage
         mp3 = pmoses(x=p.beta)(d=out, g=out1.p, s=VDD, b=VDD)
         mn5 = nbias(x=p.beta)(d=out, g=ibias, s=VSS, b=VSS)
 
-        # Load capacitance... FIXME what do we do with ya
-        CL = h.Cap(c=cl)(p=out, n=VSS)
-
         # Miller Compensation Cap
         cc = h.Cap(c=p.cc * FEMTO)(p=out, n=out1.p)
 
@@ -76,8 +68,10 @@ def opamp_inner(inp: OpAmpInput) -> OpAmpOutput:
     opamp = TwoStageOpAmp(params)
     tbparams = TbParams(
         dut=opamp,
-        VDD=VDD,
-        ibias=ibias,
+        # FIXME: make the rest of these test parameters visible to the client!
+        VDD=1800 * MILLI,
+        ibias=30 * MICRO,
+        cl=10 * PICO,
     )
     tbmodule = OpAmpTb(tbparams)
     return simulate(tbmodule)

AutoCkt/Server/autockt_server/opamps/params.py

@@ -15,6 +15,5 @@ class TbParams:
     VDD = h.Param(dtype=h.Scalar, desc="VDD voltage")
     ibias = h.Param(dtype=h.Scalar, desc="ibias current")
     # Optional
-    vicm = h.Param(
-        dtype=Optional[h.Scalar], desc="Input common-mode voltage", default=None
-    )
+    cl = h.Param(dtype=Optional[h.Scalar], desc="Load Cap", default=None)
+    vicm = h.Param(dtype=Optional[h.Scalar], desc="Input common-mode", default=None)

AutoCkt/Server/autockt_server/opamps/tb.py

@@ -19,6 +19,8 @@
 def OpAmpTb(params: TbParams) -> h.Module:
     """# Generic Op-Amp Testbench"""
 
+    # Set the default input common mode to VDD/2,
+    # if one is not provided by the params
     vicm = params.vicm or params.VDD / 2
 
     @h.module
@@ -33,6 +35,10 @@ class OpAmpTb:
         sig_n = h.Vdc(dc=vicm, ac=-0.5)(p=inp.n, n=VSS)
         Isource = h.Isrc(dc=params.ibias)(p=VSS, n=ibias)
 
+        # Load Cap
+        if params.cl is not None:
+            cl = h.Cap(c=params.cl)(p=sig_out, n=VSS)
+
         # The Op-Amp DUT
         inst = params.dut(VDD=VDD, VSS=VSS, ibias=ibias, inp=inp, out=sig_out)