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MinnowBoard MRC based support#542

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miczyg1 wants to merge 56 commits intodasharoDasharo/coreboot:dasharofrom byt_fsp_parityDasharo/coreboot:byt_fsp_parityCopy head branch name to clipboard

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Commits on Oct 8, 2024

• soc/intel/baytrail: Change NC GPIO to input pull up 20K

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• southbridge/intel/common/firmware: Use the ME file path directly

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• src/soc/intel/baytrail/northcluster.c: add NOOP set_resources to avoid an error in log

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• src/soc/intel/baytrail: Fix the FUNC_DIS bits description

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• src/device/pciexp_device.c: Control ASPM with Kconfig option

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• src/soc/intel/baytrail/Kconfig: Do not select PCIE_ASPM

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• src/soc/intel/baytrail/lpss.c: Configure INT_PIN as in FSP solution

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• soc/intel/baytrail/southcluster.c: Handle OTG and MIPI disabling properly

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• soc/intel/baytrail/pcie.c: Add support for PCIe hotplug

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• mainboard/intel/minnowmax/devicetree.cb: Use default FSP settings

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• mainboard/intel/minnowmax/devicetree.cb: Enable both SATA ports

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• mainboard/intel/minnowmax/devicetree.cb: Describe OTG controller

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• src/soc/intel/baytrail/lpss.c: Add additional programming requirements per BWG

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• soc/intel/baytrail/southcluster.c: Enable resources on LPC bridge

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• device/pci_device.c: Clear bridge VGA16 decoding control bit after probing

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• soc/intel/baytrail: Add TXE BIOS flow implementation

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• payloads/external/SeaBIOS: Add option to override CBFS location

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• soc/intel/baytrail: Put microcode and bootblock into BOOTBLOCK region

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• src/device/dram/ddr3.c: Add ECC type to DDR3 parsed data

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• mb/intel/minnowmax: Add layout with separate bootblock and manifests

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• src/mainboard/intel/minnowmax: Use SPDX license headers

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Commits on Oct 9, 2024

• 3rdparty/dasharo-blobs: Bump For MinnowBoard blobs

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• configs/config.intel_minnowmax: Add configs for regular and SB build

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• arch/x86/smbios.c: Strip leading spaces from CPU brand string

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• payloads/external/iPXE/Makefile: Use newer iPXE base revision

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• build.sh: Add options to build Intel MinnowMax

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• src/device/pciexp_device.c: switch ASPM disabling order

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• src/soc/intel/baytrail/pcie.c: set power and slot number regardless of hotplug

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• src/soc/intel/baytrail/pcie.c: update hotplug function

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• src/mainboard/intel/minnowmax/devicetree.cb: Enable HD Audio

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• src/soc/intel/baytrail: Publish device NVS to avoid ACPI errors

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• soc/intel/baytrail: Add option to disable HPET

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• src/soc/intel/baytrail/cpu.c: Sync MTRRs in later boot phase

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• src/mainboard/intel/minnowmax/Kconfig: enable S3 suspend

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• soc/intel/baytrail: Add proper UART support

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• soc/intel/baytrail/northcluster.c: Do not report the same region twice

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• src/soc/intel/baytrail/Kconfig: Disable S1

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• configs/config.intel_minnowmax_no_sb: Disable SMM BWP

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• acpi: Add support for CSRT table

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• soc/intel/baytrail/lpss: Publish CSRT table for LPSS devices

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• soc/intel/baytrail/scc: Program PCI interrupts for SCC devices

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• src/mainboard/intel/minnowmax/irqroute.h: Add missing OTG IRQ

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• src/mainboard/intel/minnowmax/gpio.c: Match Intel reference FW settings

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• soc/intel/baytrail/southcluster.c: Use generic IOAPIC init API

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• soc/intel/baytrail: Postpone setting SSC ACPI mode to APM handler

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• soc/intel/baytrail: Allow disabling SERIRQ

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• mainboard/intel/minnowmax/devicetree.cb: Put SSC and LPSS into ACPI mode

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• device/pciexp_device.c: Use disable_pcie_aspm to disable ASPM too

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• soc/intel/baytrail/Makefile.mk: Check if MANIFESTS region start is correct

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• configs/config.intel_minnowmax_sb: Disable SMM BWP

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• configs/config.intel_minnowmax: Bump to rc3

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Commits on Oct 15, 2024

• soc/intel/baytrail/Kconfig: Fix grammar

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Commits on Oct 17, 2024

• src/soc/intel/baytrail/Makefile.mk: Remove excessive comma

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• src/soc/intel/baytrail/Kconfig: Fix typo

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• src/soc/intel/baytrail/txei.c: Do not break printk string

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• src/soc/intel/baytrail/txei.c: Refactor slot calculation

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