Scala bump 2.13

Gao-Zeyu · Jan 4, 2023 · 3ac15ca · 3ac15ca
1 parent b27112d
commit 3ac15ca
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Showing 7 changed files with 15 additions and 15 deletions.
diff --git a/build.sbt b/build.sbt
@@ -1,4 +1,4 @@
 organization := "edu.berkeley.cs"
 version := "3.0"
 name := "boom"
-scalaVersion := "2.12.10"
+scalaVersion := "2.13.10"
diff --git a/src/main/scala/common/tile.scala b/src/main/scala/common/tile.scala
@@ -183,7 +183,7 @@ class BoomTileModuleImp(outer: BoomTile) extends BaseTileModuleImp(outer){
   // PTW
   val ptw  = Module(new PTW(ptwPorts.length)(outer.dcache.node.edges.out(0), outer.p))
   core.io.ptw <> ptw.io.dpath
-  ptw.io.requestor <> ptwPorts
+  ptw.io.requestor <> ptwPorts.toSeq
   hellaCachePorts += ptw.io.mem
 
   // RoCC
@@ -235,7 +235,7 @@ class BoomTileModuleImp(outer: BoomTile) extends BaseTileModuleImp(outer){
 
    // LSU IO
   val hellaCacheArb = Module(new HellaCacheArbiter(hellaCachePorts.length)(outer.p))
-  hellaCacheArb.io.requestor <> hellaCachePorts
+  hellaCacheArb.io.requestor <> hellaCachePorts.toSeq
   lsu.io.hellacache <> hellaCacheArb.io.mem
   outer.dcache.module.io.lsu <> lsu.io.dmem
 

diff --git a/src/main/scala/exu/core.scala b/src/main/scala/exu/core.scala
@@ -131,9 +131,9 @@ class BoomCore(usingTrace: Boolean)(implicit p: Parameters) extends BoomModule
                                                                    (if (usingRoCC) 1 else 0)))
   val iregister_read   = Module(new RegisterRead(
                            issue_units.map(_.issueWidth).sum,
-                           exe_units.withFilter(_.readsIrf).map(_.supportedFuncUnits),
+                           exe_units.withFilter(_.readsIrf).map(_.supportedFuncUnits).toSeq,
                            numIrfReadPorts,
-                           exe_units.withFilter(_.readsIrf).map(x => 2),
+                           exe_units.withFilter(_.readsIrf).map(x => 2).toSeq,
                            exe_units.numTotalBypassPorts,
                            jmp_unit.numBypassStages,
                            xLen))
@@ -1186,7 +1186,7 @@ class BoomCore(usingTrace: Boolean)(implicit p: Parameters) extends BoomModule
     // Connect FPIU
     ll_wbarb.io.in(1)        <> fp_pipeline.io.to_int
     // Connect FLDs
-    fp_pipeline.io.ll_wports <> exe_units.memory_units.map(_.io.ll_fresp)
+    fp_pipeline.io.ll_wports <> exe_units.memory_units.map(_.io.ll_fresp).toSeq
   }
   if (usingRoCC) {
     require(usingFPU)

diff --git a/src/main/scala/exu/execution-units/execution-unit.scala b/src/main/scala/exu/execution-units/execution-unit.scala
@@ -399,11 +399,11 @@ class ALUExeUnit(
   if (writesIrf) {
     io.iresp.valid     := iresp_fu_units.map(_.io.resp.valid).reduce(_|_)
     io.iresp.bits.uop  := PriorityMux(iresp_fu_units.map(f =>
-      (f.io.resp.valid, f.io.resp.bits.uop)))
+      (f.io.resp.valid, f.io.resp.bits.uop)).toSeq)
     io.iresp.bits.data := PriorityMux(iresp_fu_units.map(f =>
-      (f.io.resp.valid, f.io.resp.bits.data)))
+      (f.io.resp.valid, f.io.resp.bits.data)).toSeq)
     io.iresp.bits.predicated := PriorityMux(iresp_fu_units.map(f =>
-      (f.io.resp.valid, f.io.resp.bits.predicated)))
+      (f.io.resp.valid, f.io.resp.bits.predicated)).toSeq)
 
     // pulled out for critical path reasons
     // TODO: Does this make sense as part of the iresp bundle?
@@ -516,8 +516,8 @@ class FPUExeUnit(
   io.fresp.valid       := fu_units.map(_.io.resp.valid).reduce(_|_) &&
                           !(fpu.io.resp.valid && fpu.io.resp.bits.uop.fu_code_is(FU_F2I))
   io.fresp.bits.uop    := PriorityMux(fu_units.map(f => (f.io.resp.valid,
-                                                         f.io.resp.bits.uop)))
-  io.fresp.bits.data:= PriorityMux(fu_units.map(f => (f.io.resp.valid, f.io.resp.bits.data)))
+                                                         f.io.resp.bits.uop)).toSeq)
+  io.fresp.bits.data:= PriorityMux(fu_units.map(f => (f.io.resp.valid, f.io.resp.bits.data)).toSeq)
   io.fresp.bits.fflags := Mux(fpu_resp_val, fpu_resp_fflags, fdiv_resp_fflags)
 
   // Outputs (Write Port #1) -- FpToInt Queuing Unit -----------------------

diff --git a/src/main/scala/exu/fp-pipeline.scala b/src/main/scala/exu/fp-pipeline.scala
@@ -72,9 +72,9 @@ class FpPipeline(implicit p: Parameters) extends BoomModule with tile.HasFPUPara
                          ))
   val fregister_read = Module(new RegisterRead(
                          issue_unit.issueWidth,
-                         exe_units.withFilter(_.readsFrf).map(_.supportedFuncUnits),
+                         exe_units.withFilter(_.readsFrf).map(_.supportedFuncUnits).toSeq,
                          exe_units.numFrfReadPorts,
-                         exe_units.withFilter(_.readsFrf).map(x => 3),
+                         exe_units.withFilter(_.readsFrf).map(x => 3).toSeq,
                          0, // No bypass for FP
                          0,
                          fLen+1))

diff --git a/src/main/scala/exu/register-read/regfile.scala b/src/main/scala/exu/register-read/regfile.scala
@@ -145,7 +145,7 @@ class RegisterFileSynthesizable(
       val bypass_ens = bypassable_wports.map(x => x.valid &&
         x.bits.addr === read_addrs(i))
 
-      val bypass_data = Mux1H(VecInit(bypass_ens), VecInit(bypassable_wports.map(_.bits.data)))
+      val bypass_data = Mux1H(VecInit(bypass_ens.toSeq), VecInit(bypassable_wports.map(_.bits.data).toSeq))
 
       io.read_ports(i).data := Mux(bypass_ens.reduce(_|_), bypass_data, read_data(i))
     }

diff --git a/src/main/scala/exu/rename/rename-stage.scala b/src/main/scala/exu/rename/rename-stage.scala
@@ -250,7 +250,7 @@ class RenameStage(
   val remap_reqs = Wire(Vec(plWidth, new RemapReq(lregSz, pregSz)))
 
   // Generate maptable requests.
-  for ((((ren1,ren2),com),w) <- ren1_uops zip ren2_uops zip io.com_uops.reverse zipWithIndex) {
+  for ((((ren1,ren2),com),w) <- (ren1_uops zip ren2_uops zip io.com_uops.reverse).zipWithIndex) {
     map_reqs(w).lrs1 := ren1.lrs1
     map_reqs(w).lrs2 := ren1.lrs2
     map_reqs(w).lrs3 := ren1.lrs3