remove chiselName, fix for chipsalliance/chisel#2694 (riscv-boom#616)

Gao-Zeyu · Jan 4, 2023 · ed783aa · ed783aa
1 parent 570d135
commit ed783aa
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diff --git a/src/main/scala/exu/execution-units/functional-unit.scala b/src/main/scala/exu/execution-units/functional-unit.scala
@@ -18,7 +18,6 @@ package boom.exu
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.chiselName
 
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.rocket.ALU._
@@ -279,7 +278,6 @@ abstract class PipelinedFunctionalUnit(
  * @param numStages how many pipeline stages does the functional unit have
  * @param dataWidth width of the data being operated on in the functional unit
  */
-@chiselName
 class ALUUnit(isJmpUnit: Boolean = false, numStages: Int = 1, dataWidth: Int)(implicit p: Parameters)
   extends PipelinedFunctionalUnit(
     numStages = numStages,

diff --git a/src/main/scala/exu/rob.scala b/src/main/scala/exu/rob.scala
@@ -27,7 +27,6 @@ import scala.math.ceil
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.chiselName
 
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.util.Str
@@ -208,7 +207,6 @@ class DebugRobSignals(implicit p: Parameters) extends BoomBundle
  * @param numWakeupPorts number of wakeup ports to the ROB
  * @param numFpuPorts number of FPU units that will write back fflags
  */
-@chiselName
 class Rob(
   val numWakeupPorts: Int,
   val numFpuPorts: Int

diff --git a/src/main/scala/ifu/icache.scala b/src/main/scala/ifu/icache.scala
@@ -15,7 +15,6 @@ import chisel3._
 import chisel3.util._
 import chisel3.util.random._
 import chisel3.internal.sourceinfo.{SourceInfo}
-import chisel3.experimental.{chiselName}
 
 import freechips.rocketchip.config.{Parameters}
 import freechips.rocketchip.diplomacy._
@@ -103,7 +102,6 @@ object GetPropertyByHartId
  *
  * @param outer top level ICache class
  */
-@chiselName
 class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
   with HasBoomFrontendParameters
 {