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bump SOCMAKE_VERSION
docs_pages_workflow #78: Commit 1ef1b7b pushed by nookfoo
November 18, 2024 10:17 28s master
November 18, 2024 10:17 28s
Sed wor fix (#101)
docs_pages_workflow #77: Commit 22fab1a pushed by nookfoo
November 18, 2024 09:28 21s master
November 18, 2024 09:28 21s
TMRG and VIVADO fix (#100)
docs_pages_workflow #76: Commit fec973f pushed by benoitdenkinger
November 15, 2024 10:07 25s master
November 15, 2024 10:07 25s
lib_module_strip.py mode +x.
docs_pages_workflow #75: Commit 38faa1b pushed by benoitdenkinger
November 8, 2024 10:40 23s master
November 8, 2024 10:40 23s
Change sed_wor function to apply to all sources
docs_pages_workflow #74: Commit c2e1740 pushed by mksoc
November 7, 2024 16:07 23s master
November 7, 2024 16:07 23s
Bump version
docs_pages_workflow #73: Commit 0508d53 pushed by mksoc
October 30, 2024 14:19 28s master
October 30, 2024 14:19 28s
Socgen props (#98)
docs_pages_workflow #72: Commit 12225ec pushed by mksoc
October 30, 2024 13:58 20s master
October 30, 2024 13:58 20s
xcelium function never fetching sim_only files fixed (#99)
docs_pages_workflow #71: Commit cc933ff pushed by benoitdenkinger
October 29, 2024 14:56 33s master
October 29, 2024 14:56 33s
Fix sv2v replacing all Verilog files with generated ones, instead it …
docs_pages_workflow #70: Commit c5371a6 pushed by Risto97
October 28, 2024 21:40 1m 36s develop
October 28, 2024 21:40 1m 36s
Fix sv2v replacing all Verilog files with generated ones, instead it …
testing_workflow #88: Commit c5371a6 pushed by Risto97
October 28, 2024 21:40 1m 27s develop
October 28, 2024 21:40 1m 27s
copy_rtl function update (#96)
docs_pages_workflow #69: Commit f966713 pushed by benoitdenkinger
October 28, 2024 08:37 29s master
October 28, 2024 08:37 29s
Deprecate warning when only IP_NAME is passed to add_ip() resolve #88…
docs_pages_workflow #68: Commit 8ec4978 pushed by Risto97
October 27, 2024 19:02 1m 33s develop
October 27, 2024 19:02 1m 33s
Deprecate warning when only IP_NAME is passed to add_ip() resolve #88…
testing_workflow #87: Commit 8ec4978 pushed by Risto97
October 27, 2024 19:02 1m 26s develop
October 27, 2024 19:02 1m 26s
options example
testing_workflow #85: Commit 4f04d50 pushed by Risto97
October 27, 2024 08:41 2m 5s develop
October 27, 2024 08:41 2m 5s
options example
docs_pages_workflow #67: Commit 4f04d50 pushed by Risto97
October 27, 2024 08:41 1m 36s develop
October 27, 2024 08:41 1m 36s
Reintroduce configure time SystemC and UVM-SystemC build scripts (#95)
testing_workflow #84: Commit 54240e1 pushed by Risto97
October 26, 2024 20:47 1m 22s develop
October 26, 2024 20:47 1m 22s
Reintroduce configure time SystemC and UVM-SystemC build scripts (#95)
docs_pages_workflow #66: Commit 54240e1 pushed by Risto97
October 26, 2024 20:47 1m 33s develop
October 26, 2024 20:47 1m 33s
Reintroduce configure time SystemC and UVM-SystemC build scripts
testing_workflow #83: Commit 963680c pushed by Risto97
October 23, 2024 15:50 1m 23s build_scripts
October 23, 2024 15:50 1m 23s
Modelsim support (#92)
docs_pages_workflow #65: Commit 0489dcd pushed by Risto97
October 23, 2024 15:47 1m 39s develop
October 23, 2024 15:47 1m 39s
Modelsim support (#92)
testing_workflow #82: Commit 0489dcd pushed by Risto97
October 23, 2024 15:47 1m 43s develop
October 23, 2024 15:47 1m 43s
SYSTEMVERILOG_TB source file type (#94)
docs_pages_workflow #64: Commit 4a41390 pushed by benoitdenkinger
October 17, 2024 12:24 23s master
October 17, 2024 12:24 23s
make verilated library target global
docs_pages_workflow #63: Commit 6fe25e0 pushed by Risto97
October 15, 2024 19:46 1m 47s develop
October 15, 2024 19:46 1m 47s
make verilated library target global
testing_workflow #81: Commit 6fe25e0 pushed by Risto97
October 15, 2024 19:46 1m 21s develop
October 15, 2024 19:46 1m 21s
fix modelsim compile_definitions
testing_workflow #80: Commit 43078ef pushed by Risto97
October 10, 2024 20:19 2m 7s modelsim
October 10, 2024 20:19 2m 7s