SYSTEMVERILOG_TB source file type (#94)

Co-authored-by: Benoit Denkinger <[email protected]>
HEP-SoC · Oct 17, 2024 · 4a41390 · 4a41390
1 parent d1736e6
commit 4a41390
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Showing 8 changed files with 156 additions and 25 deletions.
diff --git a/cmake/firmware/add_tests.cmake b/cmake/firmware/add_tests.cmake
@@ -45,30 +45,39 @@ function(add_tests EXECUTABLE DIRECTORY)
             get_target_property(HEX_DATA_FILE ${fw_prj} HEX_DATA_${ARG_WIDTH}bit_FILE)
             add_test(
                 NAME ${fw_prj}
-                COMMAND ./${EXECUTABLE}
+                COMMAND ${EXECUTABLE}
                     ${PREFIX}firmware=${HEX_FILE}
                     ${PREFIX}firmware_text=${HEX_TEXT_FILE}
                     ${PREFIX}firmware_data=${HEX_DATA_FILE}
                     ${ARG_ARGS}
+                WORKING_DIRECTORY ${test}_test
             )
 
             add_custom_target(run_${fw_prj}
-                COMMAND ./${EXECUTABLE}
+                COMMAND ${EXECUTABLE}
                     ${PREFIX}firmware=${HEX_FILE}
                     ${PREFIX}firmware_text=${HEX_TEXT_FILE}
                     ${PREFIX}firmware_data=${HEX_DATA_FILE}
                     ${ARG_ARGS}
-                DEPENDS ${EXECUTABLE} ${fw_prj} ${ARG_DEPS}
+                DEPENDS ${fw_prj} ${ARG_DEPS}
             )
+            # Add dependency if the EXECUTABLE is a target created by add_executable
+            if(TARGET ${EXECUTABLE})
+                add_dependencies(run_${fw_prj} ${EXECUTABLE})
+            endif()
         endforeach()
     endforeach()
 
     include(ProcessorCount)
     ProcessorCount(NPROC)
     add_custom_target(check
         COMMAND ${CMAKE_CTEST_COMMAND} -j${NPROC}
-        DEPENDS ${test_list} ${EXECUTABLE}
+        DEPENDS ${test_list} ${ARG_DEPS}
     )
+    # Add dependency if the EXECUTABLE is a target created by add_executable
+    if(TARGET ${EXECUTABLE})
+        add_dependencies(check ${EXECUTABLE})
+    endif()
 
     format_string_spacing(formatted_test_msg "${_test_msg}" "  ;  ")
 

diff --git a/cmake/hwip.cmake b/cmake/hwip.cmake
@@ -227,6 +227,31 @@ function(get_ip_rtl_sources OUT_VAR IP_LIB)
     set(${OUT_VAR} ${SRC} PARENT_SCOPE)
 endfunction()
 
+#[[[
+# This function retrieves testbench/env-only RTL source files of a target library.
+#
+# :param OUT_VAR: The variable containing the retrieved source file.
+# :type OUT_VAR: string
+# :param IP_LIB: The target IP library.
+# :type IP_LIB: string
+#
+#]]
+function(get_ip_tb_only_rtl_sources OUT_VAR IP_LIB)
+    cmake_parse_arguments(ARG "NO_DEPS" "" "" ${ARGN})
+    set(_no_deps)
+    if(ARG_NO_DEPS)
+        set(_no_deps "NO_DEPS")
+    endif()
+
+    get_ip_sources(V_SRC ${IP_LIB} VERILOG_TB ${_no_deps})
+    get_ip_sources(VH_SRC ${IP_LIB} VHDL_TB ${_no_deps})
+    list(PREPEND VH_SRC ${V_SRC})
+    get_ip_sources(SRC ${IP_LIB} SYSTEMVERILOG_TB ${_no_deps})
+    list(PREPEND SRC ${VH_SRC})
+    list(REMOVE_DUPLICATES SRC)
+    set(${OUT_VAR} ${SRC} PARENT_SCOPE)
+endfunction()
+
 #[[[
 # This function retrieves simulation-only RTL source files of a target library.
 #

diff --git a/cmake/sim/cadence/xcelium.cmake b/cmake/sim/cadence/xcelium.cmake
@@ -4,7 +4,7 @@
 #[[[
 # Create a target for invoking Xcelium simulation on IP_LIB.
 #
-# It will create a target **run_<IP_LIB>_xcelium** that will start the xcelium simulation
+# It will create a target **run_<IP_LIB>_xcelium** that will compile, elaborate and run the xcelium simulation
 #
 # :param IP_LIB: RTL interface library, it needs to have SOURCES property set with a list of System Verilog files.
 # :type IP_LIB: INTERFACE_LIBRARY
@@ -17,7 +17,7 @@
 
 include_guard(GLOBAL)
 
-function(xcelium IP_LIB)
+function(xcelium_run IP_LIB)
     cmake_parse_arguments(ARG "GUI" "" "" ${ARGN})
     if(ARG_UNPARSED_ARGUMENTS)
         message(FATAL_ERROR "${CMAKE_CURRENT_FUNCTION} passed unrecognized argument " "${ARG_UNPARSED_ARGUMENTS}")
@@ -29,12 +29,16 @@ function(xcelium IP_LIB)
     get_target_property(BINARY_DIR ${IP_LIB} BINARY_DIR)
 
     if(ARG_GUI)
-        set(ARG_GUI -gui)
+        set(ARG_GUI -gui -access +rwc)
     else()
         unset(ARG_GUI)
     endif()
 
+    # Get RTL and TB sources
     get_ip_rtl_sources(SOURCES ${IP_LIB})
+    get_ip_tb_only_rtl_sources(TB_SOURCES ${IP_LIB})
+    list(APPEND SOURCES ${TB_SOURCES})
+
     get_ip_include_directories(SYSTEMVERILOG_INCLUDE_DIRS ${IP_LIB} SYSTEMVERILOG)
     get_ip_include_directories(VERILOG_INCLUDE_DIRS ${IP_LIB} VERILOG)
     set(INC_DIRS ${SYSTEMVERILOG_INCLUDE_DIRS} ${VERILOG_INCLUDE_DIRS})
@@ -50,7 +54,7 @@ function(xcelium IP_LIB)
         list(APPEND CMP_DEFS_ARG -D${def})
     endforeach()
 
-    add_custom_target( run_${IP_LIB}_${CMAKE_CURRENT_FUNCTION}
+    add_custom_target(${IP_LIB}_${CMAKE_CURRENT_FUNCTION}
         COMMAND xrun
         # Enable parameters without default value
         -setenv CADENCE_ENABLE_AVSREQ_44905_PHASE_1=1 -setenv CADENCE_ENABLE_AVSREQ_63188_PHASE_1=1
@@ -61,10 +65,90 @@ function(xcelium IP_LIB)
         ${ARG_GUI}
         COMMENT "Running ${CMAKE_CURRENT_FUNCTION} on ${IP_LIB}"
         DEPENDS ${SOURCES} ${IP_LIB}
-        )
+    )
+endfunction()
 
-    # add_dependencies(${IP_LIB}_${CMAKE_CURRENT_FUNCTION} ${IP_LIB})
+#[[[
+# Create a target for invoking Xcelium compilation and elaboration on IP_LIB.
+#
+# It will create a target **<IP_LIB>_xcelium_elab** that will compile, elaborate the design
+#
+# :param IP_LIB: RTL interface library, it needs to have SOURCES property set with a list of System Verilog files.
+# :type IP_LIB: INTERFACE_LIBRARY
+#
+# **Keyword Arguments**
+#
+# :keyword GUI: launch SimVision gui together with the simulation
+# :type GUI: boolean
+#]]
+function(xcelium_elab IP_LIB)
+    cmake_parse_arguments(ARG "" "ACCESS" "SETENV;DEFINES;ARGS" ${ARGN})
+    if(ARG_UNPARSED_ARGUMENTS)
+        message(FATAL_ERROR "${CMAKE_CURRENT_FUNCTION} passed unrecognized argument " "${ARG_UNPARSED_ARGUMENTS}")
+    endif()
 
-endfunction()
+    include("${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../hwip.cmake")
 
+    ip_assume_last(IP_LIB ${IP_LIB})
+    get_target_property(BINARY_DIR ${IP_LIB} BINARY_DIR)
+
+    # Get RTL and TB sources
+    get_ip_rtl_sources(SOURCES_LIST ${IP_LIB})
+    get_ip_tb_only_rtl_sources(TB_SOURCES_LIST ${IP_LIB})
+    list(APPEND SOURCES_LIST ${TB_SOURCES_LIST})
 
+    get_ip_include_directories(SYSTEMVERILOG_INCLUDE_DIRS ${IP_LIB} SYSTEMVERILOG)
+    get_ip_include_directories(VERILOG_INCLUDE_DIRS ${IP_LIB} VERILOG)
+    set(INC_DIRS ${SYSTEMVERILOG_INCLUDE_DIRS} ${VERILOG_INCLUDE_DIRS})
+
+    foreach(dir ${INC_DIRS})
+        list(APPEND INCDIR_LIST -incdir ${dir})
+    endforeach()
+    # message("ARG_SETENV: ${ARG_SETENV}")
+    foreach(var ${ARG_SETENV})
+        list(APPEND SETENV_LIST -setenv ${var})
+    endforeach()
+    # message("ARG_DEFINES: ${ARG_DEFINES}")
+    foreach(def ${ARG_DEFINES})
+        list(APPEND DEFINES_LIST -define ${def})
+    endforeach()
+
+    if(${TIMESCALE_ARG})
+        set(TIMESCALE_ARG -timescale ${TIMESCALE_ARG})
+    else()
+        set(TIMESCALE_ARG -timescale 1ps/1ps)
+    endif()
+
+    get_ip_compile_definitions(COMP_DEFS_SV ${IP_LIB} SYSTEMVERILOG)
+    get_ip_compile_definitions(COMP_DEFS_V ${IP_LIB} VERILOG) # TODO Add VHDL??
+    set(COMP_DEFS ${COMP_DEFS_SV} ${COMP_DEFS_V})
+    foreach(def ${COMP_DEFS})
+        list(APPEND CMP_DEFS_LIST -define ${def})
+    endforeach()
+
+    if(${ACCESS_ARG})
+        set(ACCESS_ARG -access ${ACCESS_ARG})
+    endif()
+
+    add_custom_target(${IP_LIB}_${CMAKE_CURRENT_FUNCTION}
+        COMMAND xrun
+        # xrun compiler options
+        ${SETENV_LIST}
+        ${DEFINES_LIST}
+        ${CMP_DEFS_LIST}
+        # SystemVerilog language constructs enabled by default
+        -sv
+        # xrun elaboration options
+        ${ACCESS_ARG}
+        ${TIMESCALE_ARG}
+        # Miscellaneous arguments
+        ${ARG_ARGS}
+        # Source files and include directories
+        ${SOURCES_LIST}
+        ${INCDIR_LIST}
+        BYPRODUCTS xcelium.d xrun.history xrun.key xrun.log
+        COMMENT "Running ${CMAKE_CURRENT_FUNCTION} on ${IP_LIB}"
+        DEPENDS ${SOURCES_LIST} ${IP_LIB}
+    )
+
+endfunction()
diff --git a/cmake/sim/cocotb/cocotb_iverilog.cmake b/cmake/sim/cocotb/cocotb_iverilog.cmake
@@ -225,7 +225,7 @@ function(cocotb_iverilog IP_LIB)
         DEPENDS ${CUSTOM_TARGET_NAME}
         COMMENT "Running cocotb simulation on ${IP_LIB}"
         WORKING_DIRECTORY ${OUTDIR}
-        )
+    )
 
     # Set the command as a property to be easily found by add_test()
     string(TOUPPER ${CUSTOM_TARGET_NAME} COCOTB_TEST_PROP)

diff --git a/cmake/sim/iverilog/iverilog.cmake b/cmake/sim/iverilog/iverilog.cmake
@@ -45,8 +45,8 @@ function(iverilog IP_LIB)
 
     # Get the IP RTL sources
     get_ip_rtl_sources(SOURCES ${IP_LIB})
-    # Where is defined V_SOURCES (if it's defined)?
-    list(PREPEND SOURCES ${V_SOURCES})
+    get_ip_tb_only_rtl_sources(TB_SOURCES ${IP_LIB})
+    list(APPEND SOURCES ${TB_SOURCES})
     # Get IP include directories
     get_ip_include_directories(SYSTEMVERILOG_INCLUDE_DIRS ${IP_LIB} SYSTEMVERILOG)
     get_ip_include_directories(VERILOG_INCLUDE_DIRS ${IP_LIB} VERILOG)

diff --git a/cmake/sim/synopsys/vcs.cmake b/cmake/sim/synopsys/vcs.cmake
@@ -17,7 +17,8 @@ function(vcs_vlogan IP_LIB)
     get_target_property(BINARY_DIR ${IP_LIB} BINARY_DIR)
 
     get_ip_rtl_sources(SOURCES ${IP_LIB})
-    list(PREPEND SOURCES ${V_SOURCES})
+    get_ip_tb_only_rtl_sources(TB_SOURCES ${IP_LIB})
+    list(APPEND SOURCES ${TB_SOURCES})
 
     get_ip_include_directories(SYSTEMVERILOG_INCLUDE_DIRS ${IP_LIB} SYSTEMVERILOG)
     get_ip_include_directories(VERILOG_INCLUDE_DIRS ${IP_LIB} VERILOG)
@@ -27,7 +28,7 @@ function(vcs_vlogan IP_LIB)
         list(APPEND ARG_INCDIRS -incdir ${dir})
     endforeach()
 
-    get_ip_compile_definitions(COMP_DEFS_SV ${IP_LIB} SYSTEMVERILOG) 
+    get_ip_compile_definitions(COMP_DEFS_SV ${IP_LIB} SYSTEMVERILOG)
     get_ip_compile_definitions(COMP_DEFS_V ${IP_LIB} VERILOG) # TODO add VHDL?
     set(COMP_DEFS ${COMP_DEFS_SV} ${COMP_DEFS_V})
     foreach(def ${COMP_DEFS})
@@ -55,7 +56,7 @@ function(vcs_vlogan IP_LIB)
     add_custom_command(
         OUTPUT ${STAMP_FILE}
         WORKING_DIRECTORY ${OUTDIR}
-        COMMAND ${VLOGAN_EXECUTABLE} 
+        COMMAND ${VLOGAN_EXECUTABLE}
             -full64 -nc -sverilog
             -sc_model ${ARG_TOP_MODULE}
             ${SOURCES}
@@ -74,7 +75,7 @@ function(vcs_vlogan IP_LIB)
     set(__VCS_LIB ${IP_LIB}__vcs)
     add_library(${__VCS_LIB} OBJECT IMPORTED)
     add_dependencies(${__VCS_LIB} ${IP_LIB}_${CMAKE_CURRENT_FUNCTION})
-    target_include_directories(${__VCS_LIB} INTERFACE 
+    target_include_directories(${__VCS_LIB} INTERFACE
         ${OUTDIR}/csrc/sysc/include)
     #target_link_libraries(${__VCS_LIB} INTERFACE -lpthread)
 
@@ -175,16 +176,16 @@ endfunction()
 #        add_custom_command(
 #            OUTPUT ${STAMP_FILE}
 #            WORKING_DIRECTORY ${OUTDIR}
-#            COMMAND ${_SYSCAN_EXECUTABLE} 
+#            COMMAND ${_SYSCAN_EXECUTABLE}
 #                -full64 -sysc=scv20
 #                ${_VCS_CFLAGS}
 #                ${SOURCES}
-#    
+#
 #            COMMAND touch ${STAMP_FILE}
 #            DEPENDS ${SOURCES} ${ARG_DEPENDS}
 #            COMMENT "Running ${CMAKE_CURRENT_FUNCTION} on ${EXEC}"
 #            )
-#    
+#
 #        add_custom_target(
 #            ${EXEC}_syscan
 #            DEPENDS ${STAMP_FILE}
@@ -201,7 +202,7 @@ endfunction()
 #    add_custom_command(
 #        OUTPUT ${STAMP_FILE} ${PROJECT_BINARY_DIR}/${EXEC}
 #        WORKING_DIRECTORY ${OUTDIR}
-#        COMMAND ${_VCS_EXECUTABLE} 
+#        COMMAND ${_VCS_EXECUTABLE}
 #            -full64 -nc -sysc=scv20
 #            sc_main
 #            -timescale=1ns/1ps

diff --git a/cmake/sim/verilator/verilate.cmake b/cmake/sim/verilator/verilate.cmake
@@ -71,14 +71,16 @@ function(verilate IP_LIB)
     endforeach()
 
     get_ip_rtl_sources(SOURCES ${IP_LIB})
-
+    get_ip_tb_only_rtl_sources(TB_SOURCES ${IP_LIB})
+    list(APPEND SOURCES ${TB_SOURCES})
+
     if(ARG_SED_WOR)
         include(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../utils/sed_wor/sed_wor.cmake)
         sed_wor(${IP_LIB} ${BINARY_DIR} "${SOURCES}")
         set(SOURCES ${SED_WOR_SOURCES})
         # unset, so argument is not further passed to verilator bin
         unset(ARG_SED_WOR)
-    endif() 
+    endif()
 
     get_ip_sim_only_sources(SIM_SOURCES ${IP_LIB})
     list(PREPEND SOURCES ${SIM_SOURCES})

diff --git a/cmake/sim/verisc/verisc_install.cmake b/cmake/sim/verisc/verisc_install.cmake
@@ -51,7 +51,17 @@ macro(verisc_build)
     find_package(veriSC ${VERSION} EXACT CONFIG
         PATHS ${ARG_VERISC_HOME} $ENV{VERISC_HOME} ${VERISC_HOME} ${INSTALL_DIR}
         NO_DEFAULT_PATH
-        )
+    )
+
+    if(NOT veriSC_FOUND)
+        message("VERISC package not found looking at:")
+        message("  ARG_VERISC_HOME: ${ARG_VERISC_HOME}")
+        message("  ENV(VERISC_HOME): $ENV{VERISC_HOME}")
+        message("  VERISC_HOME: ${VERISC_HOME}")
+        message("  INSTALL_DIR: ${INSTALL_DIR}")
+    elseif(NOT veriSC_VERSION VERSION_EQUAL ${VERSION})
+        message("veriSC_VERSION ${veriSC_VERSION} not matching requested version ${VERSION}")
+    endif()
 
     set(VERISC_HOME "${veriSC_DIR}/../../../")