Tool : Intel Quartus Prime Pro Edition
FPGA Device : Stratix 10 (1SG280HU1F50E2LG)
Board : Stratix 10 GX SI Development Kit
This project was done during the last month of my internship at Intel Microelectronics (M) Sdn Bhd. It was my first time using an FPGA and Verilog HDL, I had to self-learned Verilog from zero in a very short time. Plus very limited guidance was given and this project was done in rush, that's why the codes might look ridiculous.
My supervisor emphasized on my learning and the experience I gained from this project more than the result or the deliverables of the project, and therefore most of the time I was exploring the FPGA features and the Verilog language instead of doing the real work or polishing the result. I did gain a lot of new knowledge and helpful experience from this project despite the final objectives of the project were not completed, and I am very thankful to my supervisor for assigning me this project and supervising me.