Core slicing prototype

This tutorial will walk you through building and executing two versions of our core slicing prototype: one with desired security properties in RISC-V, and another for performance evaluation in x86.

RISC-V prototype

🚀 Quick start

Jump to 👉 quick-start if you do not want to compile from source code.

⌛ 🔧 Build from source

Follow 👉 build tutorial to build from source code.

👎 Limitations

There are some limitations of using QEMU-based emulation, such as:

• ⏰ Timestamp from log is not useful since it is under QEMU.
• 🚧 Slice cache will always show zero value for cache controller registers since the cache emulation is unimplemented.
• 📺 UART-0 is assigned to slice-0, UART-1 is reserved for normal harts to use before they are locked into a slice, UART-2 is used by hart1 and hart2, UART2 is used by hart 3 and hart4.

Core slicing x86 prototype

Jump to 👉 slice-x86 for x86 tutorials. You need a machine with SR-IO support NIC.

Jump to 👉 slice-x86-exp