feat(XSNoCDiffTop): wrapper XSNoCTop with Difftest Interface

To apply Difftest framework for CHI NoC, we wrapper lazy XSNoCTop
inside XSNoCDiffTop when difftest enabled, and expose necessary
soc/core/difftest IOs.

When generating XSNoCDiffTop, we will also generate JsonProfile,
which support generate another DifftestEndpoint seperately.

An example usage:
make verilog GOALS="diff" RELEASE_EXTRA_ARGS="--enable-difftest
--difftest-config ZESNH" WITH_CHISELDB=0 WITH_CONSTANTIN=0 MFC=1
PLDM=1 CONFIG=XSNoCTopConfig -j200

Makefile

@@ -158,7 +158,7 @@ $(TOP_V): $(SCALA_FILE)
 	mkdir -p $(@D)
 	$(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.runMain $(FPGATOP)   \
 		--target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS)		\
-		--num-cores $(NUM_CORES) $(RELEASE_ARGS)
+		--num-cores $(NUM_CORES) $(RELEASE_ARGS) $(RELEASE_EXTRA_ARGS)
 ifeq ($(CHISEL_TARGET),systemverilog)
 	$(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)"
 	@git log -n 1 >> .__head__

src/main/scala/top/Top.scala

@@ -420,16 +420,16 @@ object TopMain extends App {
   Constantin.init(enableConstantin && !envInFPGA)
   ChiselDB.init(enableChiselDB && !envInFPGA)
 
-  val soc = if (config(SoCParamsKey).UseXSNoCTop)
-    DisableMonitors(p => LazyModule(new XSNoCTop()(p)))(config)
-  else
-    DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
-
-  Generator.execute(firrtlOpts, soc.module, firtoolOpts)
-
-  // generate difftest bundles (w/o DifftestTopIO)
-  if (enableDifftest) {
-    DifftestModule.finish("XiangShan", false)
+  if (config(SoCParamsKey).UseXSNoCTop) {
+    if (enableDifftest) {
+      Generator.execute(firrtlOpts, DisableMonitors(p => new XSNoCDiffTop()(p))(config), firtoolOpts)
+    } else {
+      val soc = DisableMonitors(p => LazyModule(new XSNoCTop()(p)))(config)
+      Generator.execute(firrtlOpts, soc.module, firtoolOpts)
+    }
+  } else {
+    val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
+    Generator.execute(firrtlOpts, soc.module, firtoolOpts)
   }
 
   FileRegisters.write(fileDir = "./build", filePrefix = "XSTop.")

src/main/scala/top/XSNoCTop.scala

@@ -34,6 +34,9 @@ import freechips.rocketchip.util.{AsyncQueueSource, AsyncQueueParams}
 import chisel3.experimental.{annotate, ChiselAnnotation}
 import sifive.enterprise.firrtl.NestedPrefixModulesAnnotation
 
+import difftest.common.DifftestWiring
+import difftest.util.Profile
+
 class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter
 {
   override lazy val desiredName: String = "XSTop"
@@ -209,3 +212,38 @@ class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter
 
   lazy val module = new XSNoCTopImp(this)
 }
+
+class XSNoCDiffTop(implicit p: Parameters) extends Module {
+  override val desiredName: String = "XSDiffTop"
+  val l_soc = LazyModule(new XSNoCTop())
+  val soc = Module(l_soc.module)
+
+  // Expose XSTop IOs outside, i.e. io
+  def exposeIO(data: Data, name: String): Unit = {
+    val dummy = IO(chiselTypeOf(data)).suggestName(name)
+    dummy <> data
+  }
+  def exposeOptionIO(data: Option[Data], name: String): Unit = {
+    if (data.isDefined) {
+      val dummy = IO(chiselTypeOf(data.get)).suggestName(name)
+      dummy <> data.get
+    }
+  }
+  exposeIO(l_soc.clint, "clint")
+  exposeIO(l_soc.debug, "debug")
+  exposeIO(l_soc.plic, "plic")
+  exposeIO(l_soc.beu, "beu")
+  exposeIO(l_soc.nmi, "nmi")
+  soc.clock := clock
+  soc.reset := reset.asAsyncReset
+  exposeIO(soc.soc_clock, "soc_clock")
+  exposeIO(soc.soc_reset, "soc_reset")
+  exposeIO(soc.io, "io")
+  exposeOptionIO(soc.noc_clock, "noc_clock")
+  exposeOptionIO(soc.noc_reset, "noc_reset")
+  exposeOptionIO(soc.imsic_axi4lite, "imsic_axi4lite")
+
+  DifftestWiring.createAndConnectExtraIOs()
+  Profile.generateJson("XiangShan")
+}
+