Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

style(frontend): manually wrap some line #3791

Merged
merged 1 commit into from
Oct 28, 2024
Merged

style(frontend): manually wrap some line #3791

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
12 changes: 4 additions & 8 deletions src/main/scala/xiangshan/frontend/BPU.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -21,9 +21,7 @@ import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import scala.math.min
import utility._
import utils._
import xiangshan._
import xiangshan.backend.decode.ImmUnion

trait HasBPUConst extends HasXSParameter {
val MaxMetaBaseLength = if (!env.FPGAPlatform) 512 else 256 // TODO: Reduce meta length
Expand Down Expand Up @@ -555,9 +553,8 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H

val s1_ghv_wens = (0 until HistoryLength).map(n =>
(0 until numBr).map(b =>
s1_ghist_ptr_dup(0).value === (CGHPtr(false.B, n.U) + b.U).value && resp.s1.shouldShiftVec(0)(b) && s1_valid_dup(
0
)
s1_ghist_ptr_dup(0).value === (CGHPtr(false.B, n.U) + b.U).value &&
resp.s1.shouldShiftVec(0)(b) && s1_valid_dup(0)
)
)
val s1_ghv_wdatas = (0 until HistoryLength).map(n =>
Expand Down Expand Up @@ -666,9 +663,8 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H

val s2_ghv_wens = (0 until HistoryLength).map(n =>
(0 until numBr).map(b =>
s2_ghist_ptr_dup(0).value === (CGHPtr(false.B, n.U) + b.U).value && resp.s2.shouldShiftVec(0)(
b
) && s2_redirect_dup(0)
s2_ghist_ptr_dup(0).value === (CGHPtr(false.B, n.U) + b.U).value &&
resp.s2.shouldShiftVec(0)(b) && s2_redirect_dup(0)
)
)
val s2_ghv_wdatas = (0 until HistoryLength).map(n =>
Expand Down
3 changes: 0 additions & 3 deletions src/main/scala/xiangshan/frontend/Composer.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -17,11 +17,8 @@
package xiangshan.frontend

import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import utility._
import utils._
import xiangshan._

class Composer(implicit p: Parameters) extends BasePredictor with HasBPUConst with HasPerfEvents {
val (components, resp) = getBPDComponents(io.in.bits.resp_in(0), p)
Expand Down
3 changes: 0 additions & 3 deletions src/main/scala/xiangshan/frontend/FTB.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -19,11 +19,8 @@ package xiangshan.frontend
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import os.copy
import scala.{Tuple2 => &}
import scala.math.min
import utility._
import utils._
import xiangshan._

trait FTBParams extends HasXSParameter with HasBPUConst {
Expand Down
1 change: 0 additions & 1 deletion src/main/scala/xiangshan/frontend/FauFTB.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,6 @@ import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import scala.{Tuple2 => &}
import utility._
import utils._
import xiangshan._

trait FauFTBParams extends HasXSParameter with HasBPUConst {
Expand Down
1 change: 0 additions & 1 deletion src/main/scala/xiangshan/frontend/Frontend.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,6 @@ import freechips.rocketchip.diplomacy.LazyModule
import freechips.rocketchip.diplomacy.LazyModuleImp
import org.chipsalliance.cde.config.Parameters
import utility._
import utils._
import xiangshan._
import xiangshan.backend.fu.PFEvent
import xiangshan.backend.fu.PMP
Expand Down
3 changes: 0 additions & 3 deletions src/main/scala/xiangshan/frontend/FrontendBundle.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -18,11 +18,8 @@ package xiangshan.frontend

import chisel3._
import chisel3.util._
import java.util.ResourceBundle.Control
import org.chipsalliance.cde.config.Parameters
import scala.math._
import utility._
import utils._
import xiangshan._
import xiangshan.backend.fu.PMPRespBundle
import xiangshan.cache.mmu.TlbResp
Expand Down
4 changes: 0 additions & 4 deletions src/main/scala/xiangshan/frontend/IFU.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -19,15 +19,11 @@ package xiangshan.frontend

import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.RVCDecoder
import org.chipsalliance.cde.config.Parameters
import utility._
import utility.ChiselDB
import utils._
import xiangshan._
import xiangshan.backend.GPAMemEntry
import xiangshan.backend.fu.PMPReqBundle
import xiangshan.backend.fu.PMPRespBundle
import xiangshan.cache.mmu._
import xiangshan.frontend.icache._

Expand Down
2 changes: 0 additions & 2 deletions src/main/scala/xiangshan/frontend/ITTAGE.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -21,9 +21,7 @@ import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import scala.{Tuple2 => &}
import scala.math.min
import scala.util.matching.Regex
import utility._
import utils._
import xiangshan._

trait ITTageParams extends HasXSParameter with HasBPUParameter {
Expand Down
2 changes: 0 additions & 2 deletions src/main/scala/xiangshan/frontend/PreDecode.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -17,11 +17,9 @@
package xiangshan.frontend

import chisel3._
import chisel3.util
import chisel3.util._
import freechips.rocketchip.rocket.ExpandedInstruction
import freechips.rocketchip.rocket.RVCDecoder
import java.lang.reflect.Parameter
import org.chipsalliance.cde.config.Parameters
import utility._
import utils._
Expand Down
1 change: 0 additions & 1 deletion src/main/scala/xiangshan/frontend/SC.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,6 @@ import org.chipsalliance.cde.config.Parameters
import scala.{Tuple2 => &}
import scala.math.min
import utility._
import utils._
import xiangshan._

trait HasSCParameter extends TageParams {}
Expand Down
3 changes: 0 additions & 3 deletions src/main/scala/xiangshan/frontend/Tage.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -19,12 +19,9 @@ package xiangshan.frontend
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import os.followLink
import scala.{Tuple2 => &}
import scala.math.min
import scala.util.matching.Regex
import utility._
import utils._
import xiangshan._

trait TageParams extends HasBPUConst with HasXSParameter {
Expand Down
2 changes: 0 additions & 2 deletions src/main/scala/xiangshan/frontend/WrBypass.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -19,9 +19,7 @@ import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import utility._
import utils._
import xiangshan._
import xiangshan.cache.mmu.CAMTemplate

class WrBypass[T <: Data](
gen: T,
Expand Down
5 changes: 4 additions & 1 deletion src/main/scala/xiangshan/frontend/newRAS.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -548,7 +548,10 @@ class RAS(implicit p: Parameters) extends BasePredictor {
}.elsewhen(io.commit_valid && (distanceBetween(io.commit_meta_TOSW, BOS) > 2.U)) {
BOS := specPtrDec(io.commit_meta_TOSW)
}
XSError(io.commit_valid && (distanceBetween(io.commit_meta_TOSW,BOS) > 2.U), "The use of inference queue of the RAS module has unexpected situations")
XSError(
io.commit_valid && (distanceBetween(io.commit_meta_TOSW, BOS) > 2.U),
"The use of inference queue of the RAS module has unexpected situations"
)

when(io.redirect_valid) {
TOSR := io.redirect_meta_TOSR
Expand Down
Loading