MicroSoc cleanup

src/main/scala/vexiiriscv/Param.scala

@@ -437,7 +437,7 @@ class ParamSimple(){
     r.mkString("_")
   }
 
-  def addOptions(parser: scopt.OptionParser[Unit]): Unit = {
+  def addOptions(parser: scopt.OptionParser[Unit]) = {
     import parser._
     opt[Int]("xlen") action { (v, c) => xlen = v }
     opt[Int]("decoders") action { (v, c) => decoders = v }

src/main/scala/vexiiriscv/soc/micro/MicroSocGen.scala

@@ -1,7 +1,6 @@
 package vexiiriscv.soc.micro
 
 import spinal.core._
-import scala.collection.mutable.ArrayBuffer
 
 
 object MicroSocGen extends App{
@@ -15,26 +14,6 @@ object MicroSocGen extends App{
   val report = SpinalVerilog(new MicroSoc(p))
 }
 
-object MicroSocSynt extends App{
-  import spinal.lib.eda.bench._
-  val rtls = ArrayBuffer[Rtl]()
-  rtls += Rtl(SpinalVerilog{
-    val p = new MicroSocParam()
-    new MicroSoc(p) {
-      socCtrl.systemClk.setName("clk")
-      setDefinitionName("MicroSoc")
-    }
-  })
-
-  val targets = ArrayBuffer[Target]()
-  //  targets ++=  XilinxStdTargets(withFMax = true, withArea = true)
-  //  targets ++= AlteraStdTargets()
-  targets ++= EfinixStdTargets(withFMax = true, withArea = true)
-
-  Bench(rtls, targets)
-}
-
-
 
 
 

src/main/scala/vexiiriscv/soc/micro/MicroSocParam.scala

@@ -20,12 +20,13 @@ class MicroSocParam {
   // This is a command line parser utility, so you can customize the SoC using command line arguments to feed parameters
   def addOptions(parser: scopt.OptionParser[Unit]): Unit = {
     import parser._
-    vexii.addOptions(parser)
-    socCtrl.addOptions(parser)
     opt[Int]("ram-bytes") action { (v, c) => ramBytes = v }
     opt[Int]("demo-peripheral") action { (v, c) => demoPeripheral = Some(new PeripheralDemoParam(
       ledWidth = v
     ))}
+
+    socCtrl.addOptions(parser)
+    vexii.addOptions(parser)
   }
 
   // After modifying the attributes of this class, you need to call the legalize function to check / fix it is fine.

src/main/scala/vexiiriscv/soc/micro/MicroSocSim.scala

@@ -28,9 +28,10 @@ object MicroSocSim extends App{
     opt[String]("load-elf") action { (v, c) => elf = new File(v) }
     opt[Unit]("trace-konata") action { (v, c) => traceKonata = true }
     opt[Unit]("check-rvls") action { (v, c) => withRvlsCheck = true }
-    p.addOptions(this)
     sim.addOptions(this)
+    p.addOptions(this)
   }.parse(args, Unit).nonEmpty)
+  p.legalize()
 
 
   sim.compile(new MicroSoc(p){

src/main/scala/vexiiriscv/soc/micro/Misc.scala

@@ -0,0 +1,25 @@
+package vexiiriscv.soc.micro
+
+import spinal.core.SpinalVerilog
+
+import scala.collection.mutable.ArrayBuffer
+
+object MicroSocSynt extends App{
+  import spinal.lib.eda.bench._
+  val rtls = ArrayBuffer[Rtl]()
+  rtls += Rtl(SpinalVerilog{
+    val p = new MicroSocParam()
+    new MicroSoc(p) {
+      socCtrl.systemClk.setName("clk")
+      setDefinitionName("MicroSoc")
+    }
+  })
+
+  val targets = ArrayBuffer[Target]()
+  //  targets ++=  XilinxStdTargets(withFMax = true, withArea = true)
+  //  targets ++= AlteraStdTargets()
+  targets ++= EfinixStdTargets(withFMax = true, withArea = true)
+
+  Bench(rtls, targets)
+}
+

src/main/scala/vexiiriscv/soc/micro/SocCtrl.scala

@@ -11,7 +11,7 @@ class SocCtrlParam{
   var systemFrequency = 100 MHz
   def withDebug = withJtagTap ||  withJtagInstruction
 
-  def addOptions(parser: scopt.OptionParser[Unit]): Unit = {
+  def addOptions(parser: scopt.OptionParser[Unit]) = {
     import parser._
     opt[Int]("system-frequency") action { (v, c) => systemFrequency = v Hz }
     opt[Boolean]("jtag-tap") action { (v, c) => withJtagTap = v  }