Move lsu service

src/main/scala/vexiiriscv/execute/lsu/LsuL1Plugin.scala

@@ -13,7 +13,7 @@ import vexiiriscv.Global
 import vexiiriscv.misc.{PerformanceCounterService, Reservation}
 import vexiiriscv.riscv.{AtomicAlu, Riscv}
 import vexiiriscv.execute._
-import vexiiriscv.fetch.{InitService, LsuL1Service, LsuService}
+import vexiiriscv.fetch.{InitService}
 import vexiiriscv.riscv.Riscv.{RVA, RVC}
 
 import scala.collection.mutable.ArrayBuffer

src/main/scala/vexiiriscv/execute/lsu/LsuPlugin.scala

@@ -21,7 +21,6 @@ import vexiiriscv.{Global, riscv}
 import vexiiriscv.execute._
 import vexiiriscv.execute.lsu.AguPlugin._
 import vexiiriscv.execute.lsu.LsuL1.HAZARD
-import vexiiriscv.fetch.{LsuL1Service, LsuService}
 
 import scala.collection.mutable.ArrayBuffer
 

src/main/scala/vexiiriscv/execute/lsu/Prefetcher.scala

@@ -3,7 +3,7 @@ package vexiiriscv.execute.lsu
 import spinal.core._
 import spinal.lib.{misc, _}
 import spinal.lib.misc.plugin.FiberPlugin
-import vexiiriscv.fetch.{Fetch, InitService, LsuService}
+import vexiiriscv.fetch.{Fetch, InitService}
 import spinal.lib.misc.pipeline._
 import vexiiriscv.Global
 import vexiiriscv.Global._

src/main/scala/vexiiriscv/execute/lsu/Service.scala

@@ -1,9 +1,33 @@
 package vexiiriscv.execute.lsu
 
+import spinal.core.Bundle
+import spinal.core.fiber.{Handle, Retainer}
+import spinal.lib._
+import spinal.lib.system.tag.PmaRegion
+
+import scala.collection.mutable.ArrayBuffer
+
 trait LsuCachelessBusProvider {
   def getLsuCachelessBus() : LsuCachelessBus
 }
 
 trait CmoService{
   def withSoftwarePrefetch : Boolean
 }
+
+case class LsuL1InvalidationCmd() extends Bundle //Empty for now
+case class LsuL1InvalidationBus() extends Bundle {
+  val cmd = Stream(LsuL1InvalidationCmd())
+}
+trait LsuService{
+  val invalidationRetainer = Retainer()
+  val invalidationPorts = ArrayBuffer[LsuL1InvalidationBus]()
+  def newInvalidationPort() = invalidationPorts.addRet(LsuL1InvalidationBus())
+  def lsuCommitProbe : Flow[LsuCommitProbe]
+  def getBlockSize : Int
+}
+
+trait LsuL1Service{
+  def withCoherency : Boolean
+  val regions = Handle[ArrayBuffer[PmaRegion]]()
+}

src/main/scala/vexiiriscv/fetch/FetchL1Plugin.scala

@@ -35,25 +35,6 @@ trait FetchL1Service{
   def fetchProbe : FetchProbe
 }
 
-case class LsuL1InvalidationCmd() extends Bundle //Empty for now
-case class LsuL1InvalidationBus() extends Bundle {
-  val cmd = Stream(LsuL1InvalidationCmd())
-}
-trait LsuService{
-  val invalidationRetainer = Retainer()
-  val invalidationPorts = ArrayBuffer[LsuL1InvalidationBus]()
-  def newInvalidationPort() = invalidationPorts.addRet(LsuL1InvalidationBus())
-  def lsuCommitProbe : Flow[LsuCommitProbe]
-  def getBlockSize : Int
-}
-
-trait LsuL1Service{
-  def withCoherency : Boolean
-  val regions = Handle[ArrayBuffer[PmaRegion]]()
-}
-
-
-
 class FetchL1Plugin(var translationStorageParameter: Any,
                     var translationPortParameter: Any,
                     var pmpPortParameter : Any,

src/main/scala/vexiiriscv/misc/TrapPlugin.scala

@@ -12,7 +12,8 @@ import vexiiriscv.riscv.Riscv._
 import vexiiriscv._
 import vexiiriscv.decode.Decode
 import vexiiriscv.decode.Decode.{INSTRUCTION_SLICE_COUNT, INSTRUCTION_SLICE_COUNT_WIDTH, INSTRUCTION_WIDTH}
-import vexiiriscv.fetch.{Fetch, FetchL1Service, InitService, LsuL1Service, LsuService, PcService}
+import vexiiriscv.execute.lsu.{LsuL1Service, LsuService}
+import vexiiriscv.fetch.{Fetch, FetchL1Service, InitService, PcService}
 import vexiiriscv.memory.AddressTranslationService
 import vexiiriscv.prediction.{HistoryPlugin, Prediction}
 import vexiiriscv.schedule.Ages