Add a few param without

SpinalHDL · Jan 14, 2025 · 9906238 · 9906238
1 parent 48073db
commit 9906238
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Showing 3 changed files with 4 additions and 2 deletions.
diff --git a/ext/NaxSoftware b/ext/NaxSoftware
diff --git a/ext/SpinalHDL b/ext/SpinalHDL
diff --git a/src/main/scala/vexiiriscv/Param.scala b/src/main/scala/vexiiriscv/Param.scala
@@ -525,6 +525,7 @@ class ParamSimple(){
     opt[Unit]("with-gshare") action { (v, c) => withGShare = true }
     opt[Unit]("with-btb") action { (v, c) => withBtb = true }
     opt[Unit]("with-ras") action { (v, c) => withRas = true }
+    opt[Unit]("without-ras") action { (v, c) => withRas = false }
     opt[Unit]("with-late-alu") action { (v, c) => withLateAlu = true; allowBypassFrom = 0; storeRs2Late = true }
     opt[Unit]("with-store-rs2-late") action { (v, c) => storeRs2Late = true }
     opt[Int]("btb-sets") action { (v, c) => btbSets = v }
@@ -556,6 +557,7 @@ class ParamSimple(){
     opt[Int]("lsu-l1-mem-data-width-min") unbounded() action { (v, c) => lsuMemDataWidthMin = v }
     opt[Unit]("lsu-l1-coherency") action { (v, c) => lsuL1Coherency = true}
     opt[Unit]("with-lsu-bypass") action { (v, c) => withLsuBypass = true }
+    opt[Unit]("without-lsu-bypass") action { (v, c) => withLsuBypass = false }
     opt[Unit]("with-iterative-shift") action { (v, c) => withIterativeShift = true }
     opt[Int]("div-radix") action { (v, c) => divRadix = v }
     opt[String]("div-impl") action { (v, c) => divImpl = v }
+5 −1		baremetal/cfu/src/crt.S
+79 −0		baremetal/driver/custom.h
+4 −4		core/src/main/scala/spinal/core/ClockDomain.scala
+11 −1		core/src/main/scala/spinal/core/Enum.scala
+2 −0		core/src/main/scala/spinal/core/Mem.scala
+81 −1		core/src/main/scala/spinal/core/MemBlackBox.scala
+4 −2		core/src/main/scala/spinal/core/Spinal.scala
+3 −1		core/src/main/scala/spinal/core/Trait.scala
+11 −0		core/src/main/scala/spinal/core/Vec.scala
+3 −3		core/src/main/scala/spinal/core/internals/ComponentEmitter.scala
+11 −0		core/src/main/scala/spinal/core/internals/Expression.scala
+94 −4		core/src/main/scala/spinal/core/internals/Phase.scala
+24 −12		core/src/main/scala/spinal/core/sim/SimBootstraps.scala
+84 −40		core/src/main/scala/spinal/core/sim/package.scala
+135 −6		lib/src/main/scala/spinal/lib/CrossClock.scala
+13 −5		lib/src/main/scala/spinal/lib/Flow.scala
+45 −3		lib/src/main/scala/spinal/lib/Stream.scala
+1 −1		lib/src/main/scala/spinal/lib/Utils.scala
+2 −1		lib/src/main/scala/spinal/lib/bus/bmb/BmbToAxi4Bridge.scala
+1 −0		lib/src/main/scala/spinal/lib/bus/bsb/sim/BsbArgents.scala
+5 −0		lib/src/main/scala/spinal/lib/bus/tilelink/Master.scala
+5 −0		lib/src/main/scala/spinal/lib/com/eth/MacRx.scala
+59 −67		lib/src/main/scala/spinal/lib/com/eth/MacTx.scala
+2 −2		lib/src/main/scala/spinal/lib/com/i2c/Misc.scala
+1 −1		lib/src/main/scala/spinal/lib/com/uart/UartCtrl.scala
+1 −1		lib/src/main/scala/spinal/lib/com/uart/UartCtrlRx.scala
+13 −13		lib/src/main/scala/spinal/lib/com/usb/phy/UsbHubLsFs.scala
+1 −1		lib/src/main/scala/spinal/lib/com/usb/phy/UsbHubPhy.scala
+2 −1		lib/src/main/scala/spinal/lib/cpu/riscv/debug/DebugTransportModuleJtag.scala
+25 −0		lib/src/main/scala/spinal/lib/eda/asic/Phases.scala
+1 −1		lib/src/main/scala/spinal/lib/misc/InterruptNode.scala
+1 −1		lib/src/main/scala/spinal/lib/misc/test/DualSimTracer.scala
+13 −0		lib/src/main/scala/spinal/lib/sim/Flow.scala
+13 −0		lib/src/main/scala/spinal/lib/sim/Stream.scala
+2 −2		lib/src/main/scala/spinal/lib/system/dma/sg2/DmaSgReadOnly.scala
+1 −1		lib/src/main/scala/spinal/lib/system/dma/sg2/DmaSgWriteOnly.scala
+4 −1		lib/src/main/scala/spinal/lib/system/dma/sg2/sim/SimCtrl.scala
+17 −11		sim/src/main/scala/spinal/sim/GhdlBackend.scala
+12 −4		sim/src/main/scala/spinal/sim/IVerilogBackend.scala
+2 −2		sim/src/main/scala/spinal/sim/SimVpi.scala
+1 −1		sim/src/main/scala/spinal/sim/VCSBackend.scala
+9 −8		sim/src/main/scala/spinal/sim/VpiBackend.scala
+1 −1		sim/src/test/scala/spinal/sim/Test2.scala
+20 −20		sim/src/test/scala/spinal/sim/TestGhdl.scala
+2 −2		sim/src/test/scala/spinal/sim/TestIVerilog.scala
+1 −1		sim/src/test/scala/spinal/sim/TestVCS.scala
+41 −0		tester/src/test/scala/spinal/core/SpinalSimWaveLocationTester.scala
+10 −8		tester/src/test/scala/spinal/lib/SpinalSimDmaSg2WriteOnlyTester.scala
+3 −3		tester/src/test/scala/spinal/lib/SpinalSimMacSgTester.scala
+266 −3		tester/src/test/scala/spinal/lib/com/eth/SpinalSimMacTester.scala
+4 −2		tester/src/test/scala/spinal/tester/scalatest/SpinalSimBmbExclusiveMonitorTester.scala
+3 −4		tester/src/test/scala/spinal/tester/scalatest/SpinalSimUsbHostTester.scala