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db | ||
greybox_tmp | ||
incremental_db | ||
output_files | ||
simulation | ||
hc_output | ||
scaler | ||
hps_isw_handoff | ||
vip | ||
*_sim | ||
.qsys_edit | ||
PLLJ_PLLSPE_INFO.txt | ||
*.bak | ||
*.orig | ||
*.rej | ||
*.qdf | ||
*.rpt | ||
*.smsg | ||
*.summary | ||
*.done | ||
*.jdi | ||
*.pin | ||
*.sof | ||
*.qws | ||
*.ppf | ||
*.ddb | ||
build_id.v | ||
c5_pin_model_dump.txt | ||
*.sopcinfo | ||
*.csv | ||
*.f | ||
*.cmp | ||
*.sip | ||
*.spd | ||
*.bsf | ||
*~ | ||
*.xml | ||
*_netlist | ||
*.cdf | ||
synth/UAReloaded/out/ |
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[submodule "synth/UAReloaded/UAReloaded-modules"] | ||
path = synth/UAReloaded/UAReloaded-modules | ||
url = [email protected]:UnAmigaReloaded-fpga/UAReloaded-modules.git |
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OPTIONS=0,112,140,96,129,40,48,56,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 |
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# nes | ||
This is a port of Luddes NES core to the MIST. See his FPGANES blog at http://fpganes.blogspot.de for details. The original source code can be found at https://github.com/strigeus/fpganes. | ||
Many changes ported from https://github.com/MiSTer-devel/NES_MiSTer. | ||
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## UnAmiga Reloaded Port | ||
Ported from the mc2 version (Victor Trucco) by Benitoss and Rampa |
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Loopy's NSF Player | ||
------------------ | ||
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Use asm6 to compile: | ||
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asm6 nsf.asm | ||
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Strip header: | ||
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dd if=nsf.bin of=nsf.rom bs=1 skip=16 count=4096 | ||
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Convert to hex: | ||
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srec_cat nsf.rom -bin -Output nsf.hex -vmem 8 |
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