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[WIP] MultiThreshold by Binary Search #687
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auphelia
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Oct 3, 2022
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When integrating the parameters to this block, this is what worked with the FINN compiler:
parameter C_BITS = C < 2 ? 1 : $clog2(C),
int BIAS = $BIAS$,
parameter O_BITS = BIAS <= 0 ? $clog2(2**N-BIAS) : 1+$clog2(BIAS >= 2**(N-1) ? BIAS : 2**N-BIAS)
…sion, no HLS support for this class required). The following functions have been removed when compared to the original Thresholding_Batch class: - get_weightstream_width_padded() needed for cppsim - get_ap_int_max_w() needed for cppsim - get_template_param_values() needed for cppsim - get_hls_compatible_threshold_tensor() needed for cppsim/hlslib - get_verilog_top_module_intf_names() already have TOP verilog module interface names I think - get_op_and_param_counts() not used anywhere - ipgen_extra_directives() needed for cppsim/hlslib Signed-off-by: Fionn O'Donohoe <[email protected]>
…reshold_binary_search class Signed-off-by: Fionn O'Donohoe <[email protected]>
…inary search class Signed-off-by: Fionn O'Donohoe <[email protected]>
Signed-off-by: Fionn O'Donohoe <[email protected]>
… data types Signed-off-by: Fionn O'Donohoe <[email protected]>
…shapes Signed-off-by: Fionn O'Donohoe <[email protected]>
Signed-off-by: Fionn O'Donohoe <[email protected]>
Signed-off-by: Fionn O'Donohoe <[email protected]>
Signed-off-by: Fionn O'Donohoe <[email protected]>
Signed-off-by: Fionn O'Donohoe <[email protected]>
Signed-off-by: Fionn O'Donohoe <[email protected]>
Signed-off-by: Fionn O'Donohoe <[email protected]>
Signed-off-by: Fionn O'Donohoe <[email protected]>
Signed-off-by: Fionn O'Donohoe <[email protected]>
Signed-off-by: Fionn O'Donohoe <[email protected]>
…gramming Signed-off-by: Fionn O'Donohoe <[email protected]>
…ion type Signed-off-by: Fionn O'Donohoe <[email protected]>
Signed-off-by: Fionn O'Donohoe <[email protected]>
…nel fold factor is present In the case where channel fold is not present (i.e. CF is 0), we saw incorrect threshold address programming. Without this commit and when no channel folding is present, this if statement is always stepped through and was damaging LSBs of the Addr signal, causing incorrect threshold address programming for a PE core. Although the logic in the if statement looks correct (i.e. programming 0 bits (clog2(CF) => 0)) and should not harm the Addr signal, it's best to avoid stepping through a case that does not exist (i.e., there is no channel folding and each channel has its own PE; therefore no extra bits needed to program multiple channel thresholds into a single PE core). Signed-off-by: Fionn O'Donohoe <[email protected]>
commit 6582235 on dev moved all custom_ops to be compatible with qonnx 0.2.0 Signed-off-by: Fionn O'Donohoe <[email protected]>
…g collision with uniform option.
…I-compatible Verilog top-level.
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…pper.
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…al blocks.
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…tion masking.
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…pped to BRAM or URAM.
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…djusting to established naming in FINN.
azizb-xlnx
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Jan 15, 2024
Applying the original BTS pull request #687 by fionnodonohoe-xlnx to add updates and bug fixes
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Creating a draft pull request to get a head start on code reviewing - some initial feedback on the structuring of the new class would be helpful, also if the methods chosen are acceptable, etc.
Already, I noticed the banners need to be updated... and there's a method that I can probably snip - get_template_param_values().
Thomas' HDL commits can be ignored from code reviewing I think.