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[MVU/VVU] Support for double-pumped DSPs #929

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8616148
[thresholding] pass O_BITS from top module to thresholding.sv core
fionnodonohoe-xlnx Nov 15, 2022
275abad
[thresholding] pass C_BITS from top module to thresholding.sv core
fionnodonohoe-xlnx Nov 15, 2022
8849c02
[thresholding] create & fill in RTL template values using FINN
fionnodonohoe-xlnx Nov 16, 2022
84704ed
[thresholding] add method get_weightstream_width()
fionnodonohoe-xlnx Nov 16, 2022
9aa7ff3
[thresholding] add method get_in/output_width()
fionnodonohoe-xlnx Nov 16, 2022
608b5da
[thresholding] add method body for code_generation_ipi()
fionnodonohoe-xlnx Nov 16, 2022
ca6e7e7
[thresholding] add method get_verilog_top_module_intf_names()
fionnodonohoe-xlnx Nov 16, 2022
7266ee9
[thresholding] retrieve axilite write sequence for runtime weight pro…
fionnodonohoe-xlnx Nov 16, 2022
f88bdbf
[thresholding] add methods for creating weight files for each simulat…
fionnodonohoe-xlnx Nov 16, 2022
560771a
[thresholding] add method generate_params()
fionnodonohoe-xlnx Nov 16, 2022
e763bf8
[thresholding] add method for preparing a Pyverilator object for RTL …
fionnodonohoe-xlnx Nov 16, 2022
84e08f1
[thresholding] add method to run rtlsim on a thresholding binary sear…
fionnodonohoe-xlnx Nov 16, 2022
b0be07a
[thresholding] add stubbed method for ipgen_singlenode_code()
fionnodonohoe-xlnx Nov 16, 2022
30d22f8
[thresholding] update class name to a more consistent naming convention
fionnodonohoe-xlnx Nov 16, 2022
3594edd
[thresholding] add fpgadataflow pytests for thresholding binary searc…
fionnodonohoe-xlnx Nov 17, 2022
0bee70d
[thresholding] add linter fixes
fionnodonohoe-xlnx Nov 17, 2022
0689c6a
[thresholding] add flake8 fixes
fionnodonohoe-xlnx Nov 17, 2022
e9a4a7b
[thresholding] change the pytest markers to omit tests from quicktest
fionnodonohoe-xlnx Nov 17, 2022
41c0b4b
[thresholding] update copyright banners of files I have added/changed
fionnodonohoe-xlnx Nov 25, 2022
71ef39b
Translate byte to parameter word addressing in AXI adapter.
preusser Dec 1, 2022
47a0cf9
Merge branch 'dev' into feature/thresholding_addressing
preusser Dec 1, 2022
bdd100f
Merge branch 'dev' into feature/thresholding
fionnodonohoe-xlnx Dec 13, 2022
d44a66c
[thresholding] remove unused attribute
fionnodonohoe-xlnx Dec 19, 2022
f79b9ec
[thresholding] remove unnecessary HLS bug prevention check
fionnodonohoe-xlnx Dec 19, 2022
7b82de2
[thresholding] align methods with hlscustom class by adding in additi…
fionnodonohoe-xlnx Dec 19, 2022
e2816d3
[thresholding] replace hardcoded tcl commands with node attributes
fionnodonohoe-xlnx Dec 19, 2022
61acc64
Merge branch 'feature/thresholding' into feature/thresholding_addressing
preusser Dec 20, 2022
bda05ae
Fix BIAS parameter specification.
preusser Dec 20, 2022
7388e76
[thresholding] remove unused ram_style attribute
fionnodonohoe-xlnx Dec 20, 2022
be1503a
First changes to custom_op for RTL-based MVAU
mmrahorovic Jan 3, 2023
e965396
[thresholding] skip test for unsupported cppsim configuration and mer…
fionnodonohoe-xlnx Jan 5, 2023
2b8a674
[thresholding] moving find_next_power_of_2() to the util suite
fionnodonohoe-xlnx Jan 5, 2023
45bb19f
[thresholding] remove find_next_power_of_2() from thresholding binary…
fionnodonohoe-xlnx Jan 5, 2023
ca00422
[thresholding] replace math functions with existing functions
fionnodonohoe-xlnx Jan 5, 2023
7f3455f
[thresholding] remove convept of mem_mode for RTL thresholding binary…
fionnodonohoe-xlnx Jan 5, 2023
4bc69f1
[thresholding] add methods needed for convertingToHls transformation
fionnodonohoe-xlnx Jan 5, 2023
3b6a198
[thresholding] add convertingToHls transformation for thresholding bi…
fionnodonohoe-xlnx Jan 5, 2023
b3800cd
[thresholding] add test for convertingToHls transformation for thresh…
fionnodonohoe-xlnx Jan 5, 2023
11464d8
[thresholding] skip tests with unsupported folding factor input
fionnodonohoe-xlnx Jan 5, 2023
e71b1c0
[thresholding] add comments for attributes
fionnodonohoe-xlnx Jan 5, 2023
3be1140
[thresholding] replace min() with signed() function
fionnodonohoe-xlnx Jan 5, 2023
e05effc
[thresholding] fix formatting from pre-commit
fionnodonohoe-xlnx Jan 5, 2023
48c3304
[thresholding] fix more flake8 formatting
fionnodonohoe-xlnx Jan 5, 2023
1e8a36c
[thresholding] remove backslashes for flake8
fionnodonohoe-xlnx Jan 5, 2023
08f1b5f
[thresholding] more flake8 fixes
fionnodonohoe-xlnx Jan 5, 2023
481d773
[thresholding] undo flake8 fixes
fionnodonohoe-xlnx Jan 5, 2023
a51bef4
[thresholding] another flake8 fix
fionnodonohoe-xlnx Jan 5, 2023
2c313ad
[thresholding] remove cppsim test file generation
fionnodonohoe-xlnx Jan 6, 2023
49bdd28
[thresholding] remove unnecessary data generation functions for simul…
fionnodonohoe-xlnx Jan 6, 2023
e663030
[thresholding] remove potentially problematic helper function
fionnodonohoe-xlnx Jan 6, 2023
42dbf23
[thresholding] implement flake8 formatting
fionnodonohoe-xlnx Jan 6, 2023
933d747
[thresholding] remove unused imports
fionnodonohoe-xlnx Jan 6, 2023
5c6dcd9
[thresholding] remove last ununsed import
fionnodonohoe-xlnx Jan 6, 2023
51acd11
[thresholding] reformat existing import
fionnodonohoe-xlnx Jan 6, 2023
9dd4e67
Merge pull request #715 from Xilinx/feature/thresholding_addressing
auphelia Jan 10, 2023
412de82
Merge branch 'dev' into feature/thresholding
auphelia Jan 18, 2023
b886a5a
[Docs] Add bin search thresholding to docs generation
auphelia Jan 18, 2023
2c3de2a
Corrected address width in Verilog wrapper for thresholding.
preusser Jan 23, 2023
7c9f5d8
[thresholding] remove bug affecting input width in top level wrapper
fionnodonohoe-xlnx Jan 23, 2023
3a0d59d
[thresholding] adjust thresholding binary search tests to use word ad…
fionnodonohoe-xlnx Jan 23, 2023
757e3a1
[thresholding] adjust typo in exception
fionnodonohoe-xlnx Jan 23, 2023
479575b
[thresholding] undo copyright header change - only needed for new files
fionnodonohoe-xlnx Jan 23, 2023
0d99b6c
[thresholding] add docstring for migrated find_next_power_of_2() func…
fionnodonohoe-xlnx Jan 23, 2023
5a77a32
[thresholding] add docstrings for methods not in base class
fionnodonohoe-xlnx Jan 23, 2023
eeed070
[thresholding] remove unused method
fionnodonohoe-xlnx Jan 23, 2023
c270868
[thresholding] remove 'return' at end of function - not needed
fionnodonohoe-xlnx Jan 27, 2023
af22177
[thresholding] remove cppsim exec_mode from test - not exercised
fionnodonohoe-xlnx Jan 27, 2023
fab120b
[thresholding] remove unused attributes
fionnodonohoe-xlnx Jan 27, 2023
5d6c964
[thresholding] adjust i/o port names on thresholding RTL wrapper
fionnodonohoe-xlnx Jan 27, 2023
bdfa6cb
[thresholding] remove duplicated test helper function
fionnodonohoe-xlnx Jan 31, 2023
6809351
[thresholding] assert on finding unsupported memory mode for threshol…
fionnodonohoe-xlnx Jan 31, 2023
4515cf7
[thresholding] precommit fix
fionnodonohoe-xlnx Jan 31, 2023
b51498e
[thresholding] precommit fix 2
fionnodonohoe-xlnx Jan 31, 2023
ff3b201
[thresholding] precommit fix 3
fionnodonohoe-xlnx Jan 31, 2023
e0e263b
Merge branch 'dev' into feature/thresholding
auphelia Jan 31, 2023
fc7e00d
[thresholding] adjust templates so that .sv files are modular and can…
fionnodonohoe-xlnx Mar 23, 2023
f530aba
[thresholding]: remove SIGN template in thresholding RTL and create p…
fionnodonohoe-xlnx Mar 23, 2023
3cd600c
[thresholding]: decouple thresholding core from axi wrapper by removi…
fionnodonohoe-xlnx Mar 23, 2023
54afa63
[thresholding]: patch in PE value to the thresholding AXI module and …
fionnodonohoe-xlnx Mar 28, 2023
29f9e1c
[thresholding]: remove reset that erases the 0th stage threshold value
fionnodonohoe-xlnx Mar 30, 2023
2c4c8e2
[thresholding]: enable PE testing of RTL threhoslding binary search node
fionnodonohoe-xlnx Mar 31, 2023
5d07a43
[thresholding]: add comment about why bipolar activations skipped for…
fionnodonohoe-xlnx Mar 31, 2023
33fadc7
Merge branch 'dev' into feature/thresholding
fionnodonohoe-xlnx Mar 31, 2023
fcf579c
fix precommit issues
fionnodonohoe-xlnx Mar 31, 2023
8265985
Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing
mmrahorovic Apr 5, 2023
6c9d1f5
[thresholding] only adjust MSB thresholding addressing bits when chan…
fionnodonohoe-xlnx Apr 5, 2023
b247ffb
[thresholding] update binary search to match qonnx 0.2.0
fionnodonohoe-xlnx Apr 5, 2023
afab9cd
[rtl custom op]: initial implementation of mvu_8sx9
mmrahorovic Apr 6, 2023
a94fc3b
[rtl custom op]: testbench for mvu_8sx9
mmrahorovic Apr 6, 2023
98f9acc
[rtl custom op]: initial implementation of flow control component for…
mmrahorovic Apr 6, 2023
96925a9
[rtl custom op]: implementation of replay buffer for mvu
mmrahorovic Apr 6, 2023
a3d1156
[rtl custom op]: testbench for mvu_8sx9_axi (including axi_wrapper & …
mmrahorovic Apr 6, 2023
2aea664
[rtl custom op]: initial implementation of verilog wrapper for mvu_8s…
mmrahorovic Apr 6, 2023
c92e4e3
Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing
mmrahorovic Apr 6, 2023
8b57849
[rtl mvu]: fix tab indentation
mmrahorovic Apr 11, 2023
5e61f42
[rtl custom op]: fix to indentation
mmrahorovic Apr 12, 2023
cbee193
[rtl custom-op]: minor changes for compiler integration
mmrahorovic Apr 12, 2023
ba5e77b
[rtl custom op]: moved testbenches to separate directory
mmrahorovic Apr 12, 2023
69310b4
[rtl custom op]: fixed output width to ACCU_WIDTH
mmrahorovic Apr 12, 2023
cfcff00
[rtl custom op]: renamed file and added generic to switch between com…
mmrahorovic Apr 12, 2023
72b5196
[rtl custom op]: renamed file and added generic to switch between com…
mmrahorovic Apr 12, 2023
7be5ce4
Defaulting BIAS and SIGNED parameters. Renaming M to K avoiding namin…
preusser Apr 17, 2023
c068bb6
[rtl mvu]: added behavioral model DSP58
mmrahorovic May 8, 2023
18f94e7
[rtl mvu]: extended flow control wrapper with additional compute core…
mmrahorovic May 8, 2023
6d4a0a7
[rtl mvu]: fix to done_len flag when SIMD dimension fully unrolled an…
mmrahorovic May 8, 2023
90c547d
[rtl mvu tb]: updated testbench
mmrahorovic May 8, 2023
0c37f1f
[builder]: added specialize_to_rtl step and changed standalone thresh…
mmrahorovic May 8, 2023
5ccb016
[builder]: added specialize_to_rtl step
mmrahorovic May 8, 2023
f099f4b
[custom op]: added custom op MatrixVectorActivation_rtl
mmrahorovic May 8, 2023
9a3b0fd
[custom op]: added additional attribute to enable conversion to RTL (…
mmrahorovic May 8, 2023
38aa930
[custom op]: modified ip-stitching and code generation
mmrahorovic May 8, 2023
4e44934
[tests]: initial version of unit test for RTL custom op and specializ…
mmrahorovic May 8, 2023
cc361d9
[rtl mvu]: specialized compute core for 4-bit weights and activations…
mmrahorovic May 8, 2023
8eefb53
[rtl mvu]: specialized compute core for > 4-bit weights and activatio…
mmrahorovic May 8, 2023
e7109e7
[fpgadataflow transform]: initial specialize_to_rtl_layers-transform …
mmrahorovic May 8, 2023
d107b4d
Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing
mmrahorovic May 9, 2023
5a868d1
[rtl mvu] fixes for latest memstream + linting
maltanar May 9, 2023
4a9cfa1
[rtl custom_op]: add support for external weights
mmrahorovic May 11, 2023
8a9ac1a
Specify clock and reset associations of bus interfaces.
preusser May 11, 2023
51bbe02
Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing
mmrahorovic May 21, 2023
3d856b7
Merge branch 'dev' into feature/dsp_packing
preusser May 23, 2023
d9b9079
[rtlmvu] More fixes for memstream and param gen
maltanar May 15, 2023
a5f2a83
[Build] apply config to only FIFO nodes in step_set_fifo_depths
maltanar May 11, 2023
08cbdc5
Revised control interface attributes.
preusser May 24, 2023
48f0c5c
Merge branch 'dev' into feature/dsp_packing
preusser May 24, 2023
d058cc2
Mask device primitives from Verilator in favor of using behavioral code.
preusser May 24, 2023
a66f38f
[Deps] update qonnx
maltanar May 11, 2023
8f9bd04
Adding folding hints. Impl selection by case statement.
preusser May 24, 2023
8799707
Merge branch 'feature/verilator_workarounds' into feature/dsp_packing
preusser May 24, 2023
9de5ed6
Fixed behavioral sideband prediction.
preusser May 24, 2023
b6e92bb
Merge remote-tracking branch 'origin/feature/dsp_packing' into featur…
mmrahorovic May 24, 2023
239759a
[rtl mvu]: extension to allow selecting PE values that are not multip…
mmrahorovic May 24, 2023
8d3247c
[rtlmvu] Avoid unintentional verilator metacomments
maltanar May 24, 2023
ffc11d6
Merge remote-tracking branch 'origin/feature/dsp_packing' into featur…
mmrahorovic May 24, 2023
c866350
[rtl mvu]: extension to allow selecting PE values that are not multip…
mmrahorovic May 24, 2023
fd1e038
[rtl mvu axi]: updated comments on folding hints
mmrahorovic May 24, 2023
f60d4c6
[rtl custom op]: minor fixes to codegen
mmrahorovic Jun 2, 2023
a1ad304
[specialize-to-rtl]: add ram_style and rt_writeable_weights support
mmrahorovic Jun 2, 2023
2cbb68f
[rtllib]: change string type to parameter type due to Vivado error
mmrahorovic Jun 2, 2023
92eb0ed
[rtllib]: renamed variable for consistency
mmrahorovic Jun 2, 2023
471a221
Fix improper blocking assignment & linting.
preusser Jun 2, 2023
5c5dc09
[test rtl mvu]: modified/extended test cases
mmrahorovic Jun 2, 2023
b4eb9b6
[rtl mvu]: updated DSP58 >4-bit variant to lift SIMD%3==0 restriction
mmrahorovic Jun 30, 2023
ad63673
[rtl mvu]: bug fix for SIMD=1 init_leave_loads
mmrahorovic Jun 30, 2023
79e8a5e
[mvu rtl]: restrict index i to be less than 3 (within bounds of hi4)
mmrahorovic Jul 13, 2023
7be62b4
Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing
mmrahorovic Jul 17, 2023
e3493c3
Rewrite replay_buffer for input elasticity.
preusser Jun 2, 2023
44fae0c
Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing
mmrahorovic Jul 31, 2023
df51f11
Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing
mmrahorovic Aug 16, 2023
2efba68
[to-rtl]: Infer unique node names after transformation is applied
mmrahorovic Sep 5, 2023
114ea1b
[mvu rtl]: add synthesis directive to handle 'X in simulation
mmrahorovic Sep 18, 2023
79fafdb
[replay buffer rtl]: minor fix to when LEN=1 (= AWIDTH=0)
mmrahorovic Sep 18, 2023
619d9db
[mvu lut]: LUT-based MVU compute core
mmrahorovic Sep 18, 2023
090f2ac
[custom op]: add preferred_backend attribute
mmrahorovic Sep 19, 2023
ac5e82d
Ensure a minimum of two buffer slots even for length-1 sequences.
preusser Sep 21, 2023
d5ff2a2
Merge pull request #1 from Xilinx/bugfix/replay_len1
mmrahorovic Sep 21, 2023
bb94092
Merge remote-tracking branch 'origin/feature/dsp_packing' into featur…
mmrahorovic Sep 21, 2023
8515693
[rtl mvu wrapper]: support for vvu layer and rename
mmrahorovic Sep 21, 2023
cf28d78
[mvu vvu tb]: modified testbench to also support testing VVU on DSP58
mmrahorovic Sep 21, 2023
2617c39
[axi wrapper]: minor modification to comment description
mmrahorovic Sep 21, 2023
8ca5fe7
[mvu axi]: add support for VVU on DSP58
mmrahorovic Sep 21, 2023
32d6338
[mvu vvu axi]: renamed file for consistency purposes
mmrahorovic Sep 21, 2023
031406d
[mvu 8sx9]: added support for VVU on DSP58, resolved PyVerilator-caus…
mmrahorovic Sep 21, 2023
e2c1f15
[mvu vvu 8sx9]: renamed compute core for consistency
mmrahorovic Sep 21, 2023
adb5869
[axi wrapper]: changed parameter to localparam
mmrahorovic Sep 21, 2023
f54d438
[axi]: added support for LUT-based VVU
mmrahorovic Sep 21, 2023
a4e2ac7
[mvu vvu 8sx9]: minor change to list of generics
mmrahorovic Sep 21, 2023
40ad0b4
[mvu lut]: added support for VVU
mmrahorovic Sep 21, 2023
30fcb5b
[mvu vvu lut]: renamed file for consistency
mmrahorovic Sep 21, 2023
cb43438
Revert to proper address truncation without generation bit.
preusser Sep 21, 2023
b4b69f3
remove deletd/renamed files
mmrahorovic Sep 21, 2023
14c5fa9
[mvu vvu 8sx9]: renamed for consistency
mmrahorovic Sep 21, 2023
3a37588
[mvu vvu axi]: changes for renamed module
mmrahorovic Sep 21, 2023
afe36ba
[mvu vvu wrapper]: convert localparam to param
mmrahorovic Sep 25, 2023
e4f2f9e
[mvau-rtl custom-op]: bugfix to instantiate memstreamer, modified ren…
mmrahorovic Sep 25, 2023
b49b79a
[specialize to rtl]: fix to changed attribute name and added support …
mmrahorovic Sep 25, 2023
9bdba03
Adding core for DSP48 backport.
preusser Sep 19, 2023
2cf1ef7
[mvu rtl core]: added support for signed activations for DSP48-based …
mmrahorovic Sep 25, 2023
ab8d4a8
[rtl mvu custom-op]: add upper bound to SEGMENTLEN equal to number of…
mmrahorovic Sep 25, 2023
74eb42b
Starting on pumped DSP compute.
preusser Sep 29, 2023
d9e2fc6
Flag TODO.
preusser Sep 29, 2023
5a429fc
[mvu_vvu dsp58]: change weight input to 2D instead of 3D array
mmrahorovic Oct 13, 2023
a4a18bb
[mvu_vvu axi]: re-wire weights appropriately for VVU DSP58
mmrahorovic Oct 13, 2023
cc0737b
[mvu_vvu axi wrapper]: fix to IS_MVU parameter
mmrahorovic Oct 13, 2023
c0eff0b
[mvu_vvu tb]: WIP -- changes to self-checker and shape of input data
mmrahorovic Oct 13, 2023
d5ae2d2
Merge remote-tracking branch 'origin/feature/dsp_packing' into featur…
mmrahorovic Oct 13, 2023
4591bb8
[vvu_hls]: add flag to specify preferred backend
mmrahorovic Oct 13, 2023
ef1cbbe
[vvu rtl]: added new custom-op VVU_RTL
mmrahorovic Oct 13, 2023
62cec50
[dwc pw]: added new custom-op SDWC operating on SWG with parallel win…
mmrahorovic Oct 13, 2023
511f835
[transformation]: extended InsertDWC transformation to instantiate a …
mmrahorovic Oct 13, 2023
4d949d6
[custom op]: added 2 new custom-ops
mmrahorovic Oct 13, 2023
05751c4
[VVU_RTL test]: added test for RTL-based VVU, which includes testing …
mmrahorovic Oct 13, 2023
6d4ee08
[mvu vvu axi]: minor bugfixes to enable VVU
mmrahorovic Nov 1, 2023
39dc27a
[mvu tb]: created separate vvu testbench and renamed mvu_vvu_axi tb
mmrahorovic Nov 1, 2023
87b25f9
[rtl-vvu custom-op]: flipped weights per SIMD-chunk to match pattern …
mmrahorovic Nov 1, 2023
1476927
[rtl vvu test]: extended testbench
mmrahorovic Nov 1, 2023
c2acd59
Merge commit '7be5ce412e5747f17fe0062769cd2cc476b5bfa4' into feature/…
mmrahorovic Nov 15, 2023
7fc173b
[RTLThres] compute obits in Python and use placeholder in template
maltanar Nov 14, 2023
9bd0744
Merge remote-tracking branch 'origin/feature/dsp_packing' into featur…
mmrahorovic Nov 15, 2023
0bb0a43
Merge remote-tracking branch 'origin/feature/vvu_dsp_packing' into fe…
mmrahorovic Nov 16, 2023
a62911c
[mvu vvu axi]: minor fix -- define mvauin_weight_t
mmrahorovic Nov 20, 2023
4d4c61b
[specialize_to_rtl step]: add transformation to infer RTL-VVU
mmrahorovic Nov 20, 2023
612ed8f
[rtl vvu custom op]: clean-up of unused functions
mmrahorovic Nov 20, 2023
0b31a88
[folding]: first attempt to extend folding transformation to parallel…
mmrahorovic Nov 20, 2023
92bc515
[to-rtl transformation]: extended with additional checker to ensure t…
mmrahorovic Nov 20, 2023
31914b1
[build steps]: move specialize_to_rtl step to be applied after conver…
mmrahorovic Nov 27, 2023
fe97dae
Merge remote-tracking branch 'origin/feature/vvu_dsp_packing' into fe…
mmrahorovic Nov 27, 2023
fa1d116
[Test] fix data layout for golden/ret comparison in RTL MVU test
maltanar Nov 24, 2023
becaac7
[RTLCustomOp] IP packaging fixes for pDWC+VVU, fix linting too
maltanar Nov 24, 2023
e0c6c26
Merge remote-tracking branch 'upstream/feature/dwc' into feature/vvu_…
mmrahorovic Nov 27, 2023
cf7f494
[mvu vvu axi]: minor bugfixes to enable VVU
mmrahorovic Nov 1, 2023
5ffc221
[mvu vvu axi]: minor fix -- define mvauin_weight_t
mmrahorovic Nov 20, 2023
d573043
Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing
mmrahorovic Nov 27, 2023
40d652c
[rtl mvu op]: minor fix to chain length estimation and enabled behavi…
mmrahorovic Nov 29, 2023
9e0e333
Merge remote-tracking branch 'origin/feature/dsp_packing' into featur…
mmrahorovic Nov 29, 2023
977ce9b
Merge remote-tracking branch 'origin/feature/vvu_dsp_packing' into fe…
mmrahorovic Nov 29, 2023
3a1d9d2
[mvu vvu axi]: minor changes to enable double-pumped DSPs for uneven …
mmrahorovic Nov 29, 2023
493bcfe
[axi wrapper]: add port for double-clock
mmrahorovic Nov 29, 2023
58f191e
[builder]: add flag for enabling pumped compute
mmrahorovic Dec 1, 2023
f435aed
[hls custom op]: add clk2x interface
mmrahorovic Dec 1, 2023
4a8ff59
[mvu rtl]: add pumped compute attribute and fill out template accordi…
mmrahorovic Dec 1, 2023
f38fd6b
[stitched ip]: wire up clk2x interface
mmrahorovic Dec 1, 2023
078888a
[mvu vvu axi]: removed SIMD%2 constraint for double-pumped DSP58
mmrahorovic Dec 1, 2023
bbcbb5a
[builder]: minor fix to attribute naming
mmrahorovic Dec 1, 2023
b72d00d
[stitched-ip]: minor fixes to creating valid stitched-ip with ap_clk2…
mmrahorovic Dec 3, 2023
04f5863
[rtl-vvu]: add stitching support for pumped compute, minor fix to seg…
mmrahorovic Dec 3, 2023
9b80ac1
Prevent output register slice from operating in unnecessary ping-pong…
preusser Dec 3, 2023
60f483a
[mvu vvu axi]: verilator BLKLOOPINIT-error workaround
mmrahorovic Dec 7, 2023
23fb64f
[mvu vvu axi]: sign extend output tdata (byte-aligned)
mmrahorovic Dec 8, 2023
fdca45b
[mvu-rtl]: default seglen to 1 for now
mmrahorovic Dec 11, 2023
45074d9
update test config
mmrahorovic Dec 11, 2023
0ed3681
updated test config
mmrahorovic Dec 12, 2023
c396425
[rtlsim]: use pyverilator util functions
mmrahorovic Dec 13, 2023
538852d
[mvu vvu axi]: fix multiple driver error
mmrahorovic Dec 13, 2023
7e5306c
Mitigate hold time issues on feed from fast clock net.
preusser Dec 18, 2023
256931f
toggle P and Vld only when no backpressure is applied
mmrahorovic Dec 18, 2023
020c4e0
change naming
mmrahorovic Dec 18, 2023
7e12ae4
Reworking pumped DSP integration with simplified enable computation.
preusser Dec 19, 2023
6e98bac
[rtlsim]: use pyverilator util functions
mmrahorovic Dec 13, 2023
5dd74ad
[mvu vvu axi]: sign extend output tdata (byte-aligned)
mmrahorovic Dec 8, 2023
b20410b
[mvu core]: dsp48 convert unpacked array to packed array to work arou…
mmrahorovic Jan 8, 2024
1c2cc0c
[mvu axi]: update list of deduced parameters
mmrahorovic Jan 8, 2024
eeb3cea
[mvu custom-op]: remove lut-based implementation and update compute c…
mmrahorovic Jan 8, 2024
0813d14
[mvu axi]: remove LUT-based compute core
mmrahorovic Jan 8, 2024
4892d66
[hls custom-op]: enable reset in sim
mmrahorovic Jan 11, 2024
44f6e0f
[test mvu rtl]: updated test flow (DSP58 only)
mmrahorovic Jan 11, 2024
9b2cceb
[mvu vvu axi]: reworked flow control and backpressure handling by tpr…
mmrahorovic Jan 11, 2024
ee9f027
Adding DSP48E1 support for 8-bit compute. Todo: finer core differenti…
preusser Jan 31, 2024
3ab8296
Adding DSP48E1 support for 4-bit compute. Todo: finer core differenti…
preusser Jan 31, 2024
d5cd44c
Merge remote-tracking branch 'origin/feature/dsp_packing' into featur…
mmrahorovic Feb 6, 2024
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[thresholding] create & fill in RTL template values using FINN
Signed-off-by: Fionn O'Donohoe <[email protected]>
fionnodonohoe-xlnx committed Nov 17, 2022
commit 8849c026b780c152dd51c0e007c5f72bdca4808c
16 changes: 8 additions & 8 deletions finn-rtllib/thresholding/hdl/thresholding.sv
Original file line number Diff line number Diff line change
@@ -43,7 +43,7 @@
* threshold configuration relies on a channel address prefix. Inputs are
* accompanied by a channel selector.
*****************************************************************************/
module thresholding #(
module $MODULE_NAME$ #(
int unsigned N, // output precision
int unsigned M, // input/threshold precision
int unsigned C, // number of channels
@@ -68,7 +68,7 @@ module thresholding #(
// Input Stream
input logic ivld,
input logic [C_BITS-1:0] icnl, // Ignored for C == 1
input logic signed [M -1:0] idat,
input logic $SIGN$ [M -1:0] idat,

// Output Stream
output logic ovld,
@@ -80,7 +80,7 @@ module thresholding #(
typedef struct packed {
logic vld; // Valid data identification
logic [C_BITS-1:0] cnl; // Channel
logic signed [M -1:0] val; // Original input value
logic $SIGN$ [M -1:0] val; // Original input value
logic [0:N-1] res; // Assembling result with valid prefix [0:stage] after stage #stage
} pipe_t;
uwire pipe_t pipe[0:N];
@@ -91,21 +91,21 @@ module thresholding #(
for(genvar stage = 0; stage < N; stage++) begin : genStages

// Threshold Memory
uwire signed [M-1:0] thresh;
uwire $SIGN$ [M-1:0] thresh;
if(1) begin : blkUpdate

// Write control: local select from global address
uwire we = twe && tws[stage];
if((C == 1) && (stage == 0)) begin
logic signed [M-1:0] Thresh = 'x;
logic $SIGN$ [M-1:0] Thresh = 'x;
always_ff @(posedge clk) begin
if(rst) Thresh <= 'x;
else if(we) Thresh <= twd;
end
assign thresh = Thresh;
end
else begin
logic signed [M-1:0] Threshs[C * 2**stage];
logic $SIGN$ [M-1:0] Threshs[C * 2**stage];
uwire [$clog2(C)+stage-1:0] wa = twa[$left(twa):N-stage];
uwire [$clog2(C)+stage-1:0] ra;
if(C > 1) assign ra[stage+:C_BITS] = pipe[stage].cnl;
@@ -117,7 +117,7 @@ module thresholding #(
end

// Read
logic signed [M-1:0] RdReg;
logic $SIGN$ [M-1:0] RdReg;
always_ff @(posedge clk) begin
if(en) RdReg <= Threshs[ra];
end
@@ -153,4 +153,4 @@ module thresholding #(
assign ocnl = pipe[N].cnl;
assign odat = pipe[N].res + BIAS;

endmodule : thresholding
endmodule : $MODULE_NAME$
6 changes: 3 additions & 3 deletions finn-rtllib/thresholding/hdl/thresholding_axi.sv
Original file line number Diff line number Diff line change
@@ -32,7 +32,7 @@
* @author Thomas B. Preußer <[email protected]>
*****************************************************************************/

module thresholding_axi #(
module $MODULE_NAME_AXI$ #(
int unsigned N, // output precision
int unsigned M, // input/threshold precision
int unsigned C, // Channels
@@ -191,12 +191,12 @@ module thresholding_axi #(
end

// Core Thresholding Module
thresholding #(.N(N), .M(M), .C(C), .BIAS(BIAS), .O_BITS(O_BITS), .C_BITS(C_BITS)) core (
$MODULE_NAME$ #(.N(N), .M(M), .C(C), .BIAS(BIAS), .O_BITS(O_BITS), .C_BITS(C_BITS)) core (
.clk, .rst,
.twe, .twa, .twd,
.en,
.ivld, .icnl, .idat,
.ovld, .ocnl(), .odat
);

endmodule : thresholding_axi
endmodule : $MODULE_NAME_AXI$
14 changes: 7 additions & 7 deletions finn-rtllib/thresholding/hdl/thresholding_axi_wrapper.v
Original file line number Diff line number Diff line change
@@ -32,11 +32,11 @@
* @author Thomas B. Preußer <[email protected]>
*****************************************************************************/

module thresholding_axi_wrapper #(
parameter N, // output precision
parameter M, // input/threshold precision
parameter C, // Channels
int BIAS = 0, // offsetting the output [0, 2^N-1) -> [-BIAS, 2^N-1 - BIAS)
module $MODULE_NAME_AXI_WRAPPER$ #(
parameter N = $N$, // output precision
parameter M = $M$, // input/threshold precision
parameter C = $C$, // Channels
int BIAS = $BIAS$, // offsetting the output [0, 2^N-1) -> [-BIAS, 2^N-1 - BIAS)

parameter C_BITS = C < 2 ? 1 : $clog2(C),
parameter O_BITS = BIAS > 0?
@@ -83,7 +83,7 @@ module thresholding_axi_wrapper #(
output [((O_BITS+7)/8)*8-1:0] m_axis_tdata
);

thresholding_axi #(.N(N), .M(M), .C(C), .BIAS(BIAS), .O_BITS(O_BITS)) inst (
$MODULE_NAME_AXI$ #(.N(N), .M(M), .C(C), .BIAS(BIAS), .O_BITS(O_BITS)) inst (
//- Global Control ------------------
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
@@ -124,4 +124,4 @@ module thresholding_axi_wrapper #(
.m_axis_tdata(m_axis_tdata)
);

endmodule : thresholding_axi_wrapper
endmodule : $MODULE_NAME_AXI_WRAPPER$
99 changes: 99 additions & 0 deletions src/finn/custom_op/fpgadataflow/thresholding_binary_search.py
Original file line number Diff line number Diff line change
@@ -26,6 +26,7 @@
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

import os
from qonnx.core.datatype import DataType

from finn.custom_op.fpgadataflow.hlscustomop import HLSCustomOp
@@ -85,6 +86,7 @@ def get_nodeattr_types(self):
# weight data from the weight FIFOs.
"runtime_writeable_weights": ("i", False, 0, {0, 1}),
"gen_top_module": ("s", False, ""),
"activation_bias": ("i", False, 0),
}
my_attrs.update(super().get_nodeattr_types())
return my_attrs
@@ -174,6 +176,103 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name):
"""
return

# Get the integer from the DataType and string-ify it
# This assumes that the data is in the form "INTx" or similar
def conv_datatype_to_str(self, data_type):
# Handle the case that an int is passed to the function
if isinstance(data_type, int):
return str(data_type)
return str(DataType[data_type].bitwidth())

def prepare_codegen_rtl_values(self):
"""All dictionary values produced in this function are to replace
their key value(s) in the RTL template files"""
code_gen_dict = {}

# Identify the module names
code_gen_dict["$MODULE_NAME$"] = [self.get_verilog_top_module_name()]
code_gen_dict["$MODULE_NAME_AXI$"] = [self.get_verilog_top_module_name() + "_axi"]
code_gen_dict["$MODULE_NAME_AXI_WRAPPER$"] = [self.get_verilog_top_module_name() + "_axi_wrapper"]
# Set the top module name - AXI wrapper
code_gen_dict["$TOP_MODULE$"] = code_gen_dict["$MODULE_NAME_AXI_WRAPPER$"]

# Identify the module variables
output_data_type = self.get_nodeattr("outputDataType") # output precision
input_data_type = self.get_nodeattr("inputDataType") # input/threshold precision
num_channels = self.get_nodeattr("NumChannels") # number of channels
bias = self.get_nodeattr("activation_bias") # activation bias value

code_gen_dict["$N$"] = [self.conv_datatype_to_str(output_data_type)] # output precision
code_gen_dict["$M$"] = [self.conv_datatype_to_str(input_data_type)] # input/threshold precision
code_gen_dict["$C$"] = [self.conv_datatype_to_str(num_channels)] # number of channels
code_gen_dict["$BIAS$"] = [self.conv_datatype_to_str(bias)] # activation bias value

# Is the input datatype signed or unsigned? The thresholding core needs to know this
if self.get_input_datatype().min() < 0:
code_gen_dict["$SIGN$"] = ["signed"]
else:
code_gen_dict["$SIGN$"] = ["unsigned"]

return code_gen_dict

def get_rtl_file_list(self):
return ["thresholding.sv",
"thresholding_axi.sv",
"thresholding_axi_wrapper.v"]

def get_rtl_file_paths(self):
rtl_root_dir = os.environ["FINN_ROOT"] + "/finn-rtllib/thresholding/hdl/"
rtl_file_list = self.get_rtl_file_list()
rtl_file_paths = [rtl_root_dir + file for file in rtl_file_list]
return rtl_file_paths

def get_rtl_template_data(self, path):
with open(path, "r") as f:
template = f.read()
return template

def fill_in_rtl_template_data(self, replace_dict, template_data):
template_data_cp = template_data
for key in replace_dict:
replacement_line = "\n".join(replace_dict[key])
template_data_cp = template_data_cp.replace(key, replacement_line)
return template_data_cp

def dump_rtl_data(self, dest_dir, filename, data):
with open(os.path.join(dest_dir, filename), "w") as f:
f.write(data)
return

def generate_hdl(self):
# Generate a dictionary of values to put in RTL template
code_gen_dict = self.prepare_codegen_rtl_values()

# Retrieve the destination directory for the final RTL files
code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")

for rtl_file_path in self.get_rtl_file_paths():
# read in original RTL template file
template_data = self.get_rtl_template_data(rtl_file_path)
# apply code generation to templates
data = self.fill_in_rtl_template_data(code_gen_dict, template_data)
# dump filled-in template to destination directory for compilation
file_only_path = rtl_file_path.split('/')[-1]
self.dump_rtl_data(code_gen_dir, file_only_path, data)

# Before we return - set the 'gen_top_module' attribute for use later by PyVerilator and IPI generation
self.set_nodeattr("gen_top_module", code_gen_dict["$TOP_MODULE$"][0])
return

def code_generation_ipgen(self, model, fpgapart, clk):
self.generate_hdl()

# set ipgen_path and ip_path so that HLS-Synth transformation
# and stich_ip transformation do not complain
# i.e. during the HLSSynthIP() transformation
code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
self.set_nodeattr("ipgen_path", code_gen_dir)
self.set_nodeattr("ip_path", code_gen_dir)

def generate_params(self, model, path):
return