Include files (#129)

includes: Introduced include files for Makefile and system_project

- Added include files for major drivers
- Updated scripts
- Updated testbench files
- Separated Testbenches from HDL dependency
- Updated requirements for build in docs

Signed-off-by: Istvan-Zsolt Szekely <[email protected]>

docs/user_guide/build_tb.rst

@@ -60,8 +60,12 @@ Building a test bench
 
 .. caution::
 
-   Before building any test bench, you must have the environment prepared and the
-   proper tools.
+   Before building any test bench, you must have the environment prepared each
+   time a new terminal session is started:
+
+   #. Set the HDL repository path with ``export ADI_HDL_DIR=<path to dir>``.
+
+   #. Set the Testbenches repository path with ``export ADI_TB_DIR=<path to dir>``.
 
 The way of building a test bench in Cygwin and WSL is almost the same.
 In this example, it is building the **AD7616** test bench.

library/includes/Makeinclude_axi.mk

@@ -0,0 +1,8 @@
+## Copyright 2024(c) Analog Devices, Inc.
+####################################################################################
+####################################################################################
+
+# All test-bench dependencies except test programs
+SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/m_axi_sequencer.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/s_axi_sequencer.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/reg_accessor.sv

library/includes/Makeinclude_axis.mk

@@ -0,0 +1,7 @@
+## Copyright 2024(c) Analog Devices, Inc.
+####################################################################################
+####################################################################################
+
+# All test-bench dependencies except test programs
+SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/m_axis_sequencer.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/s_axis_sequencer.sv

library/includes/Makeinclude_common.mk

@@ -0,0 +1,19 @@
+## Copyright 2024(c) Analog Devices, Inc.
+####################################################################################
+####################################################################################
+
+# Makeincludes
+include $(TB_LIBRARY_PATH)/includes/Makeinclude_axi.mk
+
+# All test-bench dependencies except test programs
+SV_DEPS += $(TB_LIBRARY_PATH)/utilities/utils.svh
+SV_DEPS += $(TB_LIBRARY_PATH)/utilities/logger_pkg.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/utilities/test_harness_env.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/drivers/common/watchdog.sv
+
+SV_DEPS += system_tb.sv
+
+ENV_DEPS += system_project.tcl
+ENV_DEPS += system_bd.tcl
+ENV_DEPS += $(ADI_TB_DIR)/scripts/adi_sim.tcl
+ENV_DEPS += $(ADI_TB_DIR)/scripts/run_sim.tcl

library/includes/Makeinclude_data_offload.mk

@@ -0,0 +1,10 @@
+## Copyright 2024(c) Analog Devices, Inc.
+####################################################################################
+####################################################################################
+
+# Makeincludes
+include $(TB_LIBRARY_PATH)/includes/Makeinclude_regmap.mk
+
+# All test-bench dependencies except test programs
+SV_DEPS += $(TB_LIBRARY_PATH)/drivers/data_offload/data_offload_api.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_data_offload_pkg.sv

library/includes/Makeinclude_dmac.mk

@@ -0,0 +1,13 @@
+## Copyright 2024(c) Analog Devices, Inc.
+####################################################################################
+####################################################################################
+
+# Makeincludes
+include $(TB_LIBRARY_PATH)/includes/Makeinclude_regmap.mk
+
+# All test-bench dependencies except test programs
+SV_DEPS += $(TB_LIBRARY_PATH)/drivers/dmac/dma_trans.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/drivers/dmac/dmac_api.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_dmac_pkg.sv
+
+SIM_LIB_DEPS := io_vip

library/includes/Makeinclude_jesd.mk

@@ -0,0 +1,14 @@
+## Copyright 2024(c) Analog Devices, Inc.
+####################################################################################
+####################################################################################
+
+# Makeincludes
+include $(TB_LIBRARY_PATH)/includes/Makeinclude_regmap.mk
+
+# All test-bench dependencies except test programs
+SV_DEPS += $(TB_LIBRARY_PATH)/drivers/jesd/adi_jesd204_pkg.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_jesd_rx_pkg.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_jesd_tx_pkg.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_jesd_tpl_pkg.sv
+
+ENV_DEPS += $(TB_LIBRARY_PATH)/drivers/jesd/jesd_exerciser.tcl

library/includes/Makeinclude_regmap.mk

@@ -0,0 +1,8 @@
+## Copyright 2024(c) Analog Devices, Inc.
+####################################################################################
+####################################################################################
+
+# All test-bench dependencies except test programs
+SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/reg_accessor.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_peripheral_pkg.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_pkg.sv

library/includes/Makeinclude_scoreboard.mk

@@ -0,0 +1,9 @@
+## Copyright 2024(c) Analog Devices, Inc.
+####################################################################################
+####################################################################################
+
+# All test-bench dependencies except test programs
+SV_DEPS += $(TB_LIBRARY_PATH)/drivers/common/mailbox.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/drivers/common/scoreboard.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/drivers/common/scoreboard_pack.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/drivers/common/x_monitor.sv

library/includes/Makeinclude_spi_engine.mk

@@ -0,0 +1,14 @@
+## Copyright 2024(c) Analog Devices, Inc.
+####################################################################################
+####################################################################################
+
+# Makeincludes
+include $(TB_LIBRARY_PATH)/includes/Makeinclude_regmap.mk
+
+# All test-bench dependencies except test programs
+SV_DEPS += $(TB_LIBRARY_PATH)/vip/adi/spi_vip/adi_spi_vip_pkg.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/vip/adi/spi_vip/s_spi_sequencer.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/drivers/spi_engine/spi_engine_instr_pkg.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_spi_engine_pkg.sv
+
+SIM_LIB_DEPS += spi_vip

library/includes/Makeinclude_tdd.mk

@@ -0,0 +1,10 @@
+## Copyright 2024(c) Analog Devices, Inc.
+####################################################################################
+####################################################################################
+
+# Makeincludes
+include $(TB_LIBRARY_PATH)/includes/Makeinclude_regmap.mk
+
+# All test-bench dependencies except test programs
+SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_tdd_gen_pkg.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_tdd_trans_pkg.sv

library/includes/Makeinclude_xcvr.mk

@@ -0,0 +1,10 @@
+## Copyright 2024(c) Analog Devices, Inc.
+####################################################################################
+####################################################################################
+
+# Makeincludes
+include $(TB_LIBRARY_PATH)/includes/Makeinclude_regmap.mk
+
+# All test-bench dependencies except test programs
+SV_DEPS += $(TB_LIBRARY_PATH)/drivers/xcvr/adi_xcvr_pkg.sv
+SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/adi_regmap_xcvr_pkg.sv

library/includes/sp_include_axi.tcl

@@ -0,0 +1,41 @@
+# ***************************************************************************
+# ***************************************************************************
+# Copyright 2024 (c) Analog Devices, Inc. All rights reserved.
+#
+# In this HDL repository, there are many different and unique modules, consisting
+# of various HDL (Verilog or VHDL) components. The individual modules are
+# developed independently, and may be accompanied by separate and unique license
+# terms.
+#
+# The user should read each of these license terms, and understand the
+# freedoms and responsibilities that he or she has by using this source/core.
+#
+# This core is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE.
+#
+# Redistribution and use of source or resulting binaries, with or without modification
+# of this file, are permitted under one of the following two license terms:
+#
+#   1. The GNU General Public License version 2 as published by the
+#      Free Software Foundation, which can be found in the top level directory
+#      of this repository (LICENSE_GPL2), and also online at:
+#      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+#
+# OR
+#
+#   2. An ADI specific BSD license, which can be found in the top level directory
+#      of this repository (LICENSE_ADIBSD), and also on-line at:
+#      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+#      This will allow to generate bit files and not release the source code,
+#      as long as it attaches to an ADI device.
+#
+# ***************************************************************************
+# ***************************************************************************
+
+# Add test files to the project
+adi_sim_project_files [list \
+  "$ad_tb_dir/library/vip/amd/m_axi_sequencer.sv" \
+  "$ad_tb_dir/library/vip/amd/s_axi_sequencer.sv" \
+  "$ad_tb_dir/library/regmaps/reg_accessor.sv" \
+]

library/includes/sp_include_axis.tcl

@@ -0,0 +1,40 @@
+# ***************************************************************************
+# ***************************************************************************
+# Copyright 2024 (c) Analog Devices, Inc. All rights reserved.
+#
+# In this HDL repository, there are many different and unique modules, consisting
+# of various HDL (Verilog or VHDL) components. The individual modules are
+# developed independently, and may be accompanied by separate and unique license
+# terms.
+#
+# The user should read each of these license terms, and understand the
+# freedoms and responsibilities that he or she has by using this source/core.
+#
+# This core is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE.
+#
+# Redistribution and use of source or resulting binaries, with or without modification
+# of this file, are permitted under one of the following two license terms:
+#
+#   1. The GNU General Public License version 2 as published by the
+#      Free Software Foundation, which can be found in the top level directory
+#      of this repository (LICENSE_GPL2), and also online at:
+#      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+#
+# OR
+#
+#   2. An ADI specific BSD license, which can be found in the top level directory
+#      of this repository (LICENSE_ADIBSD), and also on-line at:
+#      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+#      This will allow to generate bit files and not release the source code,
+#      as long as it attaches to an ADI device.
+#
+# ***************************************************************************
+# ***************************************************************************
+
+# Add test files to the project
+adi_sim_project_files [list \
+  "$ad_tb_dir/library/vip/amd/m_axis_sequencer.sv" \
+  "$ad_tb_dir/library/vip/amd/s_axis_sequencer.sv" \
+]

library/includes/sp_include_common.tcl

@@ -0,0 +1,45 @@
+# ***************************************************************************
+# ***************************************************************************
+# Copyright 2024 (c) Analog Devices, Inc. All rights reserved.
+#
+# In this HDL repository, there are many different and unique modules, consisting
+# of various HDL (Verilog or VHDL) components. The individual modules are
+# developed independently, and may be accompanied by separate and unique license
+# terms.
+#
+# The user should read each of these license terms, and understand the
+# freedoms and responsibilities that he or she has by using this source/core.
+#
+# This core is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE.
+#
+# Redistribution and use of source or resulting binaries, with or without modification
+# of this file, are permitted under one of the following two license terms:
+#
+#   1. The GNU General Public License version 2 as published by the
+#      Free Software Foundation, which can be found in the top level directory
+#      of this repository (LICENSE_GPL2), and also online at:
+#      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+#
+# OR
+#
+#   2. An ADI specific BSD license, which can be found in the top level directory
+#      of this repository (LICENSE_ADIBSD), and also on-line at:
+#      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+#      This will allow to generate bit files and not release the source code,
+#      as long as it attaches to an ADI device.
+#
+# ***************************************************************************
+# ***************************************************************************
+
+source $ad_tb_dir/library/includes/sp_include_axi.tcl
+
+# Add test files to the project
+adi_sim_project_files [list \
+  "$ad_tb_dir/library/utilities/utils.svh" \
+  "$ad_tb_dir/library/utilities/logger_pkg.sv" \
+  "$ad_tb_dir/library/utilities/test_harness_env.sv" \
+  "$ad_tb_dir/library/drivers/common/watchdog.sv" \
+  "system_tb.sv" \
+]

library/includes/sp_include_data_offload.tcl

@@ -0,0 +1,42 @@
+# ***************************************************************************
+# ***************************************************************************
+# Copyright 2024 (c) Analog Devices, Inc. All rights reserved.
+#
+# In this HDL repository, there are many different and unique modules, consisting
+# of various HDL (Verilog or VHDL) components. The individual modules are
+# developed independently, and may be accompanied by separate and unique license
+# terms.
+#
+# The user should read each of these license terms, and understand the
+# freedoms and responsibilities that he or she has by using this source/core.
+#
+# This core is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE.
+#
+# Redistribution and use of source or resulting binaries, with or without modification
+# of this file, are permitted under one of the following two license terms:
+#
+#   1. The GNU General Public License version 2 as published by the
+#      Free Software Foundation, which can be found in the top level directory
+#      of this repository (LICENSE_GPL2), and also online at:
+#      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+#
+# OR
+#
+#   2. An ADI specific BSD license, which can be found in the top level directory
+#      of this repository (LICENSE_ADIBSD), and also on-line at:
+#      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+#      This will allow to generate bit files and not release the source code,
+#      as long as it attaches to an ADI device.
+#
+# ***************************************************************************
+# ***************************************************************************
+
+source $ad_tb_dir/library/includes/sp_include_regmap.tcl
+
+# Add test files to the project
+adi_sim_project_files [list \
+  "$ad_tb_dir/library/drivers/data_offload/data_offload_api.sv" \
+  "$ad_tb_dir/library/regmaps/adi_regmap_data_offload_pkg.sv" \
+]

library/includes/sp_include_dmac.tcl

@@ -0,0 +1,43 @@
+# ***************************************************************************
+# ***************************************************************************
+# Copyright 2024 (c) Analog Devices, Inc. All rights reserved.
+#
+# In this HDL repository, there are many different and unique modules, consisting
+# of various HDL (Verilog or VHDL) components. The individual modules are
+# developed independently, and may be accompanied by separate and unique license
+# terms.
+#
+# The user should read each of these license terms, and understand the
+# freedoms and responsibilities that he or she has by using this source/core.
+#
+# This core is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE.
+#
+# Redistribution and use of source or resulting binaries, with or without modification
+# of this file, are permitted under one of the following two license terms:
+#
+#   1. The GNU General Public License version 2 as published by the
+#      Free Software Foundation, which can be found in the top level directory
+#      of this repository (LICENSE_GPL2), and also online at:
+#      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+#
+# OR
+#
+#   2. An ADI specific BSD license, which can be found in the top level directory
+#      of this repository (LICENSE_ADIBSD), and also on-line at:
+#      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+#      This will allow to generate bit files and not release the source code,
+#      as long as it attaches to an ADI device.
+#
+# ***************************************************************************
+# ***************************************************************************
+
+source $ad_tb_dir/library/includes/sp_include_regmap.tcl
+
+# Add test files to the project
+adi_sim_project_files [list \
+  "$ad_tb_dir/library/drivers/dmac/dma_trans.sv" \
+  "$ad_tb_dir/library/drivers/dmac/dmac_api.sv" \
+  "$ad_tb_dir/library/regmaps/adi_regmap_dmac_pkg.sv" \
+]