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ignore syscall instruction in x86
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Kyle-Kyle committed Apr 29, 2024
1 parent aea35a7 commit f566a9c
Showing 1 changed file with 12 additions and 1 deletion.
13 changes: 12 additions & 1 deletion angrop/arch.py
Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ def __init__(self, project, kernel_mode=False):
self.ret_insts = {b"\xc2", b"\xc3", b"\xca", b"\xcb"}
self.segment_regs = {"cs", "ds", "es", "fs", "gs", "ss"}

def block_make_sense(self, block):
def _x86_block_make_sense(self, block):
capstr = str(block.capstone).lower()
# currently, angrop does not handle "repz ret" correctly, we filter it
if any(x in capstr for x in ('cli', 'rex', 'repz ret')):
Expand All @@ -53,12 +53,23 @@ def block_make_sense(self, block):
return False
return True

def block_make_sense(self, block):
if not self._x86_block_make_sense(block):
return False
for x in block.capstone.insns:
if x.mnemonic == 'syscall':
return False
return True

class AMD64(X86):
def __init__(self, project, kernel_mode=False):
super().__init__(project, kernel_mode=kernel_mode)
self.syscall_insts = {b"\x0f\x05"} # syscall
self.segment_regs = {"cs_seg", "ds_seg", "es_seg", "fs_seg", "gs_seg", "ss_seg"}

def block_make_sense(self, block):
return self._x86_block_make_sense(block)

arm_conditional_postfix = ['eq', 'ne', 'cs', 'hs', 'cc', 'lo', 'mi', 'pl',
'vs', 'vc', 'hi', 'ls', 'ge', 'lt', 'gt', 'le', 'al']
class ARM(ROPArch):
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