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Merge branch 'main' into release/0.6
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maxcapodi78 authored and maxcapodi78 committed Jan 30, 2023
2 parents bfd146d + 7786dc5 commit 447b276
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Showing 63 changed files with 4,160 additions and 677 deletions.
4 changes: 4 additions & 0 deletions .gitignore
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Expand Up @@ -246,6 +246,10 @@ UpgradeLog*.htm
ServiceFabricBackup/
*.rptproj.bak

# Backup & orig files
*.bak
*.orig

# SQL Server files
*.mdf
# *.ldf
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2 changes: 1 addition & 1 deletion .pre-commit-config.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ repos:
- --line-length=120

- repo: https://github.com/pycqa/isort
rev: 5.11.4
rev: 5.12.0
hooks:
- id: isort
name: isort (python)
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Binary file added _unittest/example_models/T13/Coax_HFSS_v231.jpg
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15 changes: 15 additions & 0 deletions _unittest/test_00_EDB.py
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Expand Up @@ -875,6 +875,8 @@ def test_084_primitives_area(self):
assert self.edbapp.core_primitives.primitives[i].area(False) > 0
assert self.edbapp.core_primitives.primitives[i].area(True) > 0
i += 1
assert self.edbapp.core_primitives.primitives[i].bbox
assert self.edbapp.core_primitives.primitives[i].center

def test_085_short_component(self):
assert self.edbapp.core_components.short_component_pins("EU1", width=0.2e-3)
Expand Down Expand Up @@ -2148,3 +2150,16 @@ def test_131_siwave_ac_simulation_setup(self):

def test_132_via_plating_ratio_check(self):
assert self.edbapp.core_padstack.check_and_fix_via_plating()

def test_133_siwave_build_ac_prject(self):
source_path = os.path.join(local_path, "example_models", test_subfolder, "padstacks.aedb")
target_path = os.path.join(self.local_scratch.path, "test_133_simconfig.aedb")
self.local_scratch.copyfolder(source_path, target_path)
edbapp = Edb(target_path, edbversion=desktop_version)
simconfig = edbapp.new_simulation_configuration()
simconfig.solver_type = SolverType.SiwaveSYZ
simconfig.mesh_freq = "40.25GHz"
edbapp.build_simulation_project(simconfig)
setup = list(edbapp.active_cell.SimulationSetups)[0]
setup_str = [t.strip("\n\t") for t in setup.ToString().split("\r")]
assert [f for f in setup_str if "MeshFrequency" in f][0].split("=")[-1].strip("'") == simconfig.mesh_freq
15 changes: 15 additions & 0 deletions _unittest/test_00_GeometryOperators.py
Original file line number Diff line number Diff line change
Expand Up @@ -367,6 +367,21 @@ def test_orient_polygon(self):
yo.reverse()
assert x == xo
assert y == yo
x2 = [3, 3]
y2 = [1, 2]
xo2, yo2 = go.orient_polygon(x2, y2, clockwise=True)
assert x2 == xo2
assert y2 == yo2
try:
go.orient_polygon([1], [2], clockwise=True)
assert False
except ValueError as e:
assert str(e) == "'x' length must be >= 2"
try:
go.orient_polygon([1, 2, 3], [1, 2], clockwise=True)
assert False
except ValueError as e:
assert str(e) == "'y' must be same length as 'x'"

def test_is_collinear(self):
assert go.is_collinear([1, 0, 0], [1, 0, 0])
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4 changes: 3 additions & 1 deletion _unittest/test_13_LoadAEDTFile.py
Original file line number Diff line number Diff line change
Expand Up @@ -16,12 +16,14 @@
cs1 = "Coordinate_System1_231"
cs2 = "Coordinate_System2_231"
cs3 = "Coordinate_System3_231"
image_f = "Coax_HFSS_v231.jpg"
else:
test_project_name = "Coax_HFSS_t13"
cs = "Coordinate_System"
cs1 = "Coordinate_System1"
cs2 = "Coordinate_System2"
cs3 = "Coordinate_System3"
image_f = "Coax_HFSS.jpg"


def _write_jpg(design_info, scratch):
Expand Down Expand Up @@ -67,7 +69,7 @@ def test_02_check_design_info(self):
assert design_info["DesignName"] == "HFSSDesign"
assert design_info["IsSolved"] == False
jpg_file = _write_jpg(design_info, self.local_scratch.path)
assert filecmp.cmp(jpg_file, os.path.join(local_path, "example_models", test_subfolder, "Coax_HFSS.jpg"))
assert filecmp.cmp(jpg_file, os.path.join(local_path, "example_models", test_subfolder, image_f))

def test_03_check_can_load_aedt_file_with_binary_content(self):
aedt_file = os.path.join(local_path, "example_models", test_subfolder, "assembly.aedt")
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69 changes: 60 additions & 9 deletions _unittest/test_20_HFSS.py
Original file line number Diff line number Diff line change
Expand Up @@ -976,27 +976,78 @@ def test_45_terminal_port(self):
)
assert port3.name + "_T1" in self.aedtapp.excitations

@pytest.mark.skipif(desktop_version > "2022.2", reason="To Be fixed in 23R1.")
def test_45B_terminal_port(self):
self.aedtapp.insert_design("Design_Terminal_2")
self.aedtapp.solution_type = "Terminal"
box1 = self.aedtapp.modeler.create_box([-100, -100, 0], [200, 200, 5], name="gnd2", matname="copper")
box2 = self.aedtapp.modeler.create_box([-100, -100, 20], [200, 200, 25], name="sig2", matname="copper")
box1 = self.aedtapp.modeler.create_box([-100, -100, 0], [200, 200, 5], name="gnd2z", matname="copper")
box2 = self.aedtapp.modeler.create_box([-100, -100, 20], [200, 200, 25], name="sig2z", matname="copper")
box3 = self.aedtapp.modeler.create_box([-40, -40, -20], [80, 80, 10], name="box3", matname="copper")
box4 = self.aedtapp.modeler.create_box([-40, -40, 10], [80, 80, 10], name="box4", matname="copper")
boundaries = len(self.aedtapp.boundaries)

assert self.aedtapp.create_spiral_lumped_port(box1, box2)
box1.display_wireframe = True
box2.display_wireframe = True
box3.display_wireframe = True
box4.display_wireframe = True
self.aedtapp.modeler.fit_all()
portz = self.aedtapp.create_spiral_lumped_port(box1, box2)
assert portz

n_boundaries = len(self.aedtapp.boundaries)
assert n_boundaries == 3

box5 = self.aedtapp.modeler.create_box([-50, -15, 200], [150, -10, 200], name="gnd2y", matname="copper")
box6 = self.aedtapp.modeler.create_box([-50, 10, 200], [150, 15, 200], name="sig2y", matname="copper")
box5.display_wireframe = True
box6.display_wireframe = True
self.aedtapp.modeler.fit_all()
porty = self.aedtapp.create_spiral_lumped_port(box5, box6)
assert porty

n_boundaries = len(self.aedtapp.boundaries)
assert n_boundaries == 6

box7 = self.aedtapp.modeler.create_box([-15, 300, 0], [-10, 200, 100], name="gnd2x", matname="copper")
box8 = self.aedtapp.modeler.create_box([15, 300, 0], [10, 200, 100], name="sig2x", matname="copper")
box7.display_wireframe = True
box8.display_wireframe = True
self.aedtapp.modeler.fit_all()
portx = self.aedtapp.create_spiral_lumped_port(box7, box8)
assert portx

n_boundaries = len(self.aedtapp.boundaries)
assert n_boundaries == 9

# Use two boxes with different dimensions.
try:
self.aedtapp.create_spiral_lumped_port(box1, box3)
except AttributeError as e:
assert e.args[0] == "The closest faces of the two objects must be identical in shape."
else:
assert False

# Rotate box2 so that, box3 and box4 are not collinear anymore.
# Rotate box3 so that, box3 and box4 are not collinear anymore.
# Spiral lumped port can only be created based on 2 collinear objects.
box3.rotate(cs_axis="X", angle=90)
try:
self.aedtapp.create_spiral_lumped_port(box3, box4)
except AttributeError as e:
exception_raised = True
assert e.args[0] == "The two objects must have parallel adjacent faces."
assert exception_raised
else:
assert False

# Rotate back box3
# rotate them slightly so that they are still parallel, but not aligned anymore with main planes.
box3.rotate(cs_axis="X", angle=-90)
box3.rotate(cs_axis="Y", angle=5)
box4.rotate(cs_axis="Y", angle=5)
try:
self.aedtapp.create_spiral_lumped_port(box3, box4)
except AttributeError as e:
assert (
e.args[0]
== "The closest faces of the two objects must be aligned with the main planes of the reference system."
)
else:
assert False

def test_46_mesh_settings(self):
assert self.aedtapp.mesh.initial_mesh_settings
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44 changes: 36 additions & 8 deletions _unittest/test_21_Circuit.py
Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,7 @@ class TestClass(BasisTest, object):
def setup_class(self):
BasisTest.my_setup(self)
self.aedtapp = BasisTest.add_app(self, original_project_name, application=Circuit, subfolder=test_subfolder)
self.aedtapp.modeler.schematic_units = "mil"
self.circuitprj = BasisTest.add_app(self, diff_proj_name, application=Circuit, subfolder=test_subfolder)
netlist_file1 = os.path.join(local_path, "example_models", test_subfolder, netlist1)
netlist_file2 = os.path.join(local_path, "example_models", test_subfolder, netlist2)
Expand All @@ -57,12 +58,12 @@ def test_02_create_resistor(self):
assert myres.parameters["R"] == "50"

def test_03_create_capacitor(self):
mycap = self.aedtapp.modeler.schematic.create_capacitor(value=1e-12, location=[0.6, 0.2])
mycap = self.aedtapp.modeler.schematic.create_capacitor(value=1e-12, location=[1000, 2000])
assert type(mycap.id) is int
assert mycap.parameters["C"] == "1e-12"
tol = 1e-12
assert abs(mycap.pins[0].location[1] - 0.20066) < tol
assert abs(mycap.pins[0].location[0] - 0.5943600000000001) < tol
assert abs(mycap.pins[0].location[1] - 2000) < tol
assert abs(mycap.pins[0].location[0] - 800) < tol

def test_04_getpin_names(self):
mycap2 = self.aedtapp.modeler.schematic.create_capacitor(value=1e-12)
Expand Down Expand Up @@ -162,7 +163,7 @@ def test_12_connect_components(self):
portname = self.aedtapp.modeler.schematic.create_interface_port("Port1")
assert len(self.aedtapp.excitations) > 0
assert "Port1" in portname.name
assert myind.pins[0].connect_to_component(portname.pins[0])
assert myind.pins[0].connect_to_component(portname.pins[0], use_wire=True)
assert myind.pins[1].connect_to_component(myres.pins[1])
assert self.aedtapp.modeler.connect_schematic_components(myres.id, mycap.id, pinnum_first=1)
gnd = self.aedtapp.modeler.schematic.create_gnd()
Expand All @@ -185,8 +186,17 @@ def test_13_properties(self):
assert self.aedtapp.modeler.model_units

def test_14_move(self):
assert self.aedtapp.modeler.move("L100", [0, -0.00508])
assert self.aedtapp.modeler.move("L100", [0, 200], "mil")
self.aedtapp.modeler.schematic_units = "mil"
myind = self.aedtapp.modeler.schematic.create_inductor("L14", 1e-9, [400, 400])
self.aedtapp.modeler.schematic_units = "meter"
assert self.aedtapp.modeler.move("L14", [0, -0.00508])
assert myind.location == [0.01016, 0.00508]
self.aedtapp.modeler.schematic_units = "mil"
assert self.aedtapp.modeler.move(
"L14",
[0, 200],
)
assert myind.location == [400.0, 400.0]

def test_15_rotate(self):
assert self.aedtapp.modeler.rotate("IPort@Port1")
Expand Down Expand Up @@ -384,8 +394,8 @@ def test_30_create_subcircuit(self):
assert type(subcircuit.location) is list
assert type(subcircuit.id) is int
assert subcircuit.component_info
assert subcircuit.location[0] == "0.0mil"
assert subcircuit.location[1] == "0.0mil"
assert subcircuit.location[0] == 0.0
assert subcircuit.location[1] == 0.0
assert subcircuit.angle == 0.0

@pytest.mark.skipif(
Expand Down Expand Up @@ -692,3 +702,21 @@ def test_41_set_variable(self):
self.aedtapp["var_test"] = "234"
assert "var_test" in self.aedtapp.variable_manager.design_variable_names
assert self.aedtapp.variable_manager.design_variables["var_test"].expression == "234"

def test_42_auto_wire(self):
self.aedtapp.insert_design("wires")
self.aedtapp.modeler.schematic_units = "mil"
p1 = self.aedtapp.modeler.schematic.create_interface_port(name="In", location=[200, 300])
r1 = self.aedtapp.modeler.schematic.create_resistor(value=50, location=[3700, "3mm"])
l1 = self.aedtapp.modeler.schematic.create_inductor(value=1e-9, location=[1400, 3000], angle=90)
l3 = self.aedtapp.modeler.schematic.create_inductor(value=1e-9, location=[1600, 2500], angle=90)
l4 = self.aedtapp.modeler.schematic.create_inductor(value=1e-9, location=[1600, 500], angle=90)
l2 = self.aedtapp.modeler.schematic.create_inductor(value=1e-9, location=[1400, 4000], angle=0)
r2 = self.aedtapp.modeler.schematic.create_resistor(value=50, location=[3100, 3200])

assert p1.pins[0].connect_to_component(r1.pins[1], use_wire=True)
assert l1.pins[0].connect_to_component(l2.pins[0], use_wire=True)
assert l3.pins[0].connect_to_component(l2.pins[1], use_wire=True, clearance_units=2)
assert l4.pins[1].connect_to_component(l3.pins[0], use_wire=True, clearance_units=2)
assert l4.pins[0].connect_to_component(l3.pins[1], use_wire=True)
assert r1.pins[0].connect_to_component(l2.pins[0], use_wire=True)
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