splitting ecc error trigger test into two tests

chipsalliance · Jan 9, 2025 · 5158264 · 5158264
1 parent e133efd
commit 5158264
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Showing 8 changed files with 675 additions and 211 deletions.
diff --git a/src/integration/stimulus/L0_regression.yml b/src/integration/stimulus/L0_regression.yml
@@ -47,7 +47,8 @@ contents:
         - ../test_suites/pv_hash_and_sign/pv_hash_and_sign.yml
         - ../test_suites/smoke_test_pcr_signing/smoke_test_pcr_signing.yml
         - ../test_suites/smoke_test_fw_kv_backtoback_hmac/smoke_test_fw_kv_backtoback_hmac.yml
-        - ../test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.yml
+        - ../test_suites/smoke_test_ecc_errortrigger1/smoke_test_ecc_errortrigger1.yml
+        - ../test_suites/smoke_test_ecc_errortrigger2/smoke_test_ecc_errortrigger2.yml
         - ../test_suites/smoke_test_hmac_errortrigger/smoke_test_hmac_errortrigger.yml
         - ../test_suites/smoke_test_pcr_zeroize/smoke_test_pcr_zeroize.yml
         - ../test_suites/smoke_test_ahb_mux/smoke_test_ahb_mux.yml

diff --git a/src/integration/stimulus/testsuites/caliptra_top_nightly_directed_regression.yml b/src/integration/stimulus/testsuites/caliptra_top_nightly_directed_regression.yml
@@ -50,7 +50,8 @@ contents:
         - ${CALIPTRA_ROOT}/src/integration/test_suites/pv_hash_and_sign/pv_hash_and_sign.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_pcr_signing/smoke_test_pcr_signing.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_fw_kv_backtoback_hmac/smoke_test_fw_kv_backtoback_hmac.yml
-        - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ecc_errortrigger/smoke_test_ecc_errortrigger.yml
+        - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ecc_errortrigger1/smoke_test_ecc_errortrigger1.yml
+        - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ecc_errortrigger2/smoke_test_ecc_errortrigger2.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_pcr_zeroize/smoke_test_pcr_zeroize.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_ahb_mux/smoke_test_ahb_mux.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_doe_rand/smoke_test_doe_rand.yml

diff --git a/...moke_test_ecc_errortrigger/caliptra_isr.h → ...oke_test_ecc_errortrigger1/caliptra_isr.h b/...moke_test_ecc_errortrigger/caliptra_isr.h → ...oke_test_ecc_errortrigger1/caliptra_isr.h
diff --git a/...rrortrigger/smoke_test_ecc_errortrigger.c → ...ortrigger1/smoke_test_ecc_errortrigger1.c b/...rrortrigger/smoke_test_ecc_errortrigger.c → ...ortrigger1/smoke_test_ecc_errortrigger1.c
@@ -421,215 +421,6 @@ void main() {
         rst_count++;
         printf("%c",0xf6);
     }   
-    else if(rst_count == 6) {
-        // wait for ECC to be ready
-        while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0);
-
-        printf("\n TEST PCR WITH INVALID OUTPUT SIGN_R\n");
-
-        // Program ECC IV
-        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0;
-        offset = 0;
-        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) {
-            *reg_ptr++ = ecc_iv[offset++];
-        }
-
-        //Inject invalid zero sign_r
-        printf("%c",0x98);
-
-        //inject seed to kv key reg (in RTL)
-        printf("Inject PRIVKEY into KV slot 7\n");
-        privkey_inject_cmd = 0x88 + 0x7;
-        printf("%c", privkey_inject_cmd);
-
-        printf("Inject MSG into SHA512 digest\n");
-        printf("%c", 0x90);
-
-        // Enable ECC PCR SIGNING core
-        printf("\nECC PCR SIGNING\n");
-        lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_SIGNING | 
-                ((1 << ECC_REG_ECC_CTRL_PCR_SIGN_LOW) & ECC_REG_ECC_CTRL_PCR_SIGN_MASK));
-
-
-        // wait for ECC PCR SIGNING process to be done
-        wait_for_ecc_intr();
-        if ((cptra_intr_rcv.ecc_error == 0)){
-            printf("\nECC PCR r_output_outofrange error is not detected.\n");
-            printf("%c", 0x1);
-            while(1);
-        }
-
-        ecc_zeroize();
-        //Issue warm reset
-        rst_count++;
-        printf("%c",0xf6);
-    }  
-    else if(rst_count == 7) {
-        // wait for ECC to be ready
-        while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0);
-
-        printf("\n TEST PCR WITH INVALID INPUT COMMAND\n");
-
-        // Program ECC IV
-        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0;
-        offset = 0;
-        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) {
-            *reg_ptr++ = ecc_iv[offset++];
-        }
-
-        //inject seed to kv key reg (in RTL)
-        printf("Inject PRIVKEY into KV slot 7\n");
-        privkey_inject_cmd = 0x88 + 0x7;
-        printf("%c", privkey_inject_cmd);
-
-        printf("Inject MSG into SHA512 digest\n");
-        printf("%c", 0x90);
-
-        // Enable ECC PCR KEYGEN core
-        printf("\nECC PCR KEYGEN\n");
-        lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_KEYGEN | 
-                ((1 << ECC_REG_ECC_CTRL_PCR_SIGN_LOW) & ECC_REG_ECC_CTRL_PCR_SIGN_MASK));
-
-
-        // wait for ECC KEYGEN process to be done
-        wait_for_ecc_intr();
-        if ((cptra_intr_rcv.ecc_error == 0)){
-            printf("\nECC PCR invalid command error is not detected.\n");
-            printf("%c", 0x1);
-            while(1);
-        }
-
-        ecc_zeroize();
-        //Issue warm reset
-        rst_count++;
-        printf("%c",0xf6);
-    }
-    else if(rst_count == 8) {
-        // wait for ECC to be ready
-        while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0);
-
-        printf("\n TEST PCR WITH INVALID INPUT COMMAND\n");
-
-        // Program ECC IV
-        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0;
-        offset = 0;
-        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) {
-            *reg_ptr++ = ecc_iv[offset++];
-        }
-
-        //inject seed to kv key reg (in RTL)
-        printf("Inject PRIVKEY into KV slot 7\n");
-        privkey_inject_cmd = 0x88 + 0x7;
-        printf("%c", privkey_inject_cmd);
-
-        printf("Inject MSG into SHA512 digest\n");
-        printf("%c", 0x90);
-
-        // Enable ECC PCR VERIFYING core
-        printf("\nECC PCR VERIFYING\n");
-        lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_VERIFYING | 
-                ((1 << ECC_REG_ECC_CTRL_PCR_SIGN_LOW) & ECC_REG_ECC_CTRL_PCR_SIGN_MASK));
-
-
-        // wait for ECC VERIFYING process to be done
-        wait_for_ecc_intr();
-        if ((cptra_intr_rcv.ecc_error == 0)){
-            printf("\nECC PCR invalid command error is not detected.\n");
-            printf("%c", 0x1);
-            while(1);
-        }
-
-        ecc_zeroize();
-        //Issue warm reset
-        rst_count++;
-        printf("%c",0xf6);
-    }
-    else if(rst_count == 9) {
-        // wait for ECC to be ready
-        while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0);
-
-        printf("\n TEST INVALID OUTPUT SIGN_S\n");
-        // Program ECC PRIVKEY
-        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_PRIVKEY_IN_0;
-        offset = 0;
-        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_PRIVKEY_IN_11) {
-            *reg_ptr++ = ecc_privkey[offset++];
-        }
-
-        // Program ECC MSG
-        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_MSG_0;
-        offset = 0;
-        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_MSG_11) {
-            *reg_ptr++ = ecc_msg[offset++];
-        }
-
-        // Program ECC IV
-        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0;
-        offset = 0;
-        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) {
-            *reg_ptr++ = ecc_iv[offset++];
-        }
-
-        //Inject invalid zero sign_s
-        printf("%c",0x9a);
-
-        // Enable ECC SIGNING core
-        printf("\nECC SIGNING\n");
-        lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_SIGNING);
-
-        // wait for ECC SIGNING process to be done
-        wait_for_ecc_intr();
-        if ((cptra_intr_rcv.ecc_error == 0)){
-            printf("\nECC s_output_outofrange error is not detected.\n");
-            printf("%c", 0x1);
-            while(1);
-        }
-
-        ecc_zeroize();
-        //Issue warm reset
-        rst_count++;
-        printf("%c",0xf6);
-    }
-    else if(rst_count == 10) {
-        // wait for ECC to be ready
-        while((lsu_read_32(CLP_ECC_REG_ECC_STATUS) & ECC_REG_ECC_STATUS_READY_MASK) == 0);
-
-        printf("\n TEST PCR WITH INVALID OUTPUT SIGN_S\n");
-
-        // Program ECC IV
-        reg_ptr = (uint32_t*) CLP_ECC_REG_ECC_IV_0;
-        offset = 0;
-        while (reg_ptr <= (uint32_t*) CLP_ECC_REG_ECC_IV_11) {
-            *reg_ptr++ = ecc_iv[offset++];
-        }
-
-        //Inject invalid zero sign_s
-        printf("%c",0x9a);
-
-        //inject seed to kv key reg (in RTL)
-        printf("Inject PRIVKEY into KV slot 7\n");
-        privkey_inject_cmd = 0x88 + 0x7;
-        printf("%c", privkey_inject_cmd);
-
-        printf("Inject MSG into SHA512 digest\n");
-        printf("%c", 0x90);
-
-        // Enable ECC PCR SIGNING core
-        printf("\nECC PCR SIGNING\n");
-        lsu_write_32(CLP_ECC_REG_ECC_CTRL, ECC_CMD_SIGNING | 
-                ((1 << ECC_REG_ECC_CTRL_PCR_SIGN_LOW) & ECC_REG_ECC_CTRL_PCR_SIGN_MASK));
-
-
-        // wait for ECC PCR SIGNING process to be done
-        wait_for_ecc_intr();
-        if ((cptra_intr_rcv.ecc_error == 0)){
-            printf("\nECC PCR s_output_outofrange error is not detected.\n");
-            printf("%c", 0x1);
-            while(1);
-        }
-
-        ecc_zeroize();
-    }  
 
     printf("%c",0xff); //End the test
 

diff --git a/src/integration/test_suites/smoke_test_ecc_errortrigger1/smoke_test_ecc_errortrigger1.yml b/src/integration/test_suites/smoke_test_ecc_errortrigger1/smoke_test_ecc_errortrigger1.yml
@@ -0,0 +1,3 @@
+---
+seed: 1
+testname: smoke_test_ecc_errortrigger1