Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Adding companion main class to generate GCD.v verilog source #126

Merged
merged 5 commits into from
Mar 7, 2024
Merged

Adding companion main class to generate GCD.v verilog source #126

Changes from 1 commit
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
a4415ab
Adding companion main class to generate GCD.v verilog source
Martoni Mar 7, 2024
0661927
Remove verilog file if exists before generate it
Martoni Mar 7, 2024
51c49d1
Use emitSystemVerilogFile to simplify
Martoni Mar 7, 2024
149c75c
Apply suggestions from code review
jackkoenig Mar 7, 2024
a066306
Merge branch 'main' into generate_verilog
jackkoenig Mar 7, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
12 changes: 12 additions & 0 deletions src/main/scala/gcd/GCD.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@
package gcd

import chisel3._
import circt.stage.ChiselStage
jackkoenig marked this conversation as resolved.
Show resolved Hide resolved

/**
* Compute GCD using subtraction method.
Expand Down Expand Up @@ -32,3 +33,14 @@ class GCD extends Module {
io.outputGCD := x
io.outputValid := y === 0.U
}

/**
* Generate Verilog sources and save it in file GCD.v
*/
object GCD extends App {
val verilog_src = ChiselStage.emitSystemVerilog(
Copy link

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Would it not be simpler to call ChiselStage.emitSystemVerilogFile rather than emitting as a string and then writing?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Yes of course ! I didn't know about this function.
That's why it's useful to provide an example :)

new GCD(),
firtoolOpts = Array("-disable-all-randomization",
"-strip-debug-info"))
os.write(os.pwd / "GCD.v", verilog_src)
}