interconnect/ahb/AHB2Wishbone: Fix size check that is too restrictive…

…, can be <= log2_int(ahb.data_width//8).
enjoy-digital · Jan 4, 2024 · 5bbcda4 · 5bbcda4
1 parent 6a68370
commit 5bbcda4
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/litex/soc/interconnect/ahb.py b/litex/soc/interconnect/ahb.py
@@ -70,7 +70,7 @@ def __init__(self, ahb, wishbone):
         fsm.act("IDLE",
             ahb.readyout.eq(1),
             If(ahb.sel &
-              (ahb.size  == wishbone_adr_shift) &
+              (ahb.size  <= log2_int(ahb.data_width//8)) &
               (ahb.trans == TransferType.NONSEQUENTIAL),
                NextValue(wishbone.adr,   ahb.addr[wishbone_adr_shift:]),
                NextValue(wishbone.dat_w, ahb.wdata),