soc: fix typo in cpu mem_bus axi-via-wb downconvert (#1865)

Fixes: 002aad7 Signed-off-by: Gabriel Somlo <[email protected]>
enjoy-digital · Jan 1, 2024 · acf07a2 · acf07a2
1 parent 56f6198
commit acf07a2
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
@@ -1651,9 +1651,9 @@ def add_sdram(self, name="sdram", phy=None, module=None, origin=None, size=None,
                     else:
                         mem_wb  = wishbone.Interface(
                             data_width = self.cpu.mem_axi.data_width,
-                            adr_width  = 32-log2_int(mem_bus.data_width//8,
+                            adr_width  = 32-log2_int(mem_bus.data_width//8),
                             addressing = "word",
-                        ))
+                        )
                         mem_a2w = axi.AXI2Wishbone(
                             axi          = mem_bus,
                             wishbone     = mem_wb,