Merge pull request #1817 from enjoy-digital/wishbone_word_byte_addres…

…sing

Add wishbone word/byte addressing.

litex/soc/cores/cpu/blackparrot/core.py

@@ -91,7 +91,7 @@ def __init__(self, platform, variant="standard"):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
-        self.idbus        = idbus = wishbone.Interface(data_width=64, adr_width=37)
+        self.idbus        = idbus = wishbone.Interface(data_width=64, adr_width=37, addressing="word")
         self.periph_buses = [idbus]
         self.memory_buses = []
 

litex/soc/cores/cpu/cortex_m1/core.py

@@ -64,7 +64,7 @@ def __init__(self, platform, variant="standard"):
         self.cpu_params = dict(
             # Clk/Rst.
             i_HCLK      = ClockSignal("sys"),
-            i_SYSRESETn = ~(ResetSignal() | self.reset),
+            i_SYSRESETn = ~(ResetSignal("sys") | self.reset),
 
             # Control/Status.
             o_LOCKUP      = Open(),
@@ -85,7 +85,7 @@ def __init__(self, platform, variant="standard"):
             # Debug.
             p_SMALL_DEBUG  = True,
             i_DBGRESTART   = 0,
-            i_DBGRESETn    = ~(ResetSignal() | self.reset),
+            i_DBGRESETn    = ~(ResetSignal("sys") | self.reset),
             p_DEBUG_SEL    = 1, # JTAG
             o_DBGRESTARTED = Open(),
 

litex/soc/cores/cpu/cortex_m3/core.py

@@ -65,7 +65,7 @@ def __init__(self, platform, variant="standard"):
         self.cpu_params = dict(
             # Clk/Rst.
             i_HCLK      = ClockSignal("sys"),
-            i_SYSRESETn = ~(ResetSignal() | self.reset),
+            i_SYSRESETn = ~(ResetSignal("sys") | self.reset),
 
             # Control/Status.
             p_MPU_PRESENT = 0,
@@ -82,7 +82,7 @@ def __init__(self, platform, variant="standard"):
             i_CFGITCMEN = 0,  # 1 = alias ITCM at 0x0
 
             # Debug.
-            i_DBGRESETn = ~(ResetSignal() | self.reset),
+            i_DBGRESETn = ~(ResetSignal("sys") | self.reset),
 
             # Instruction Bus (AXI).
             o_AWVALIDC = ibus.aw.valid,

litex/soc/cores/cpu/cv32e40p/core.py

@@ -232,7 +232,7 @@ def __init__(self, trace_depth=16384):
 
 class TraceDebugger(LiteXModule):
     def __init__(self):
-        self.bus      = wishbone.Interface()
+        self.bus      = wishbone.Interface(data_width=32, address_width=32, addressing="word")
         self.source   = source   = stream.Endpoint([("data", 32)])
         self.trace_if = trace_if = Record(trace_layout)
 
@@ -292,8 +292,8 @@ def __init__(self, pads=None):
         if pads is None:
             pads = Record(self.jtag_layout)
         self.pads = pads
-        self.dmbus = wishbone.Interface()
-        self.sbbus = wishbone.Interface()
+        self.dmbus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
+        self.sbbus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
         dmbus = Record(obi_layout)
         sbbus = Record(obi_layout)
 
@@ -382,8 +382,8 @@ def __init__(self, platform, variant="standard"):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
-        self.ibus         = wishbone.Interface()
-        self.dbus         = wishbone.Interface()
+        self.ibus         = wishbone.Interface(data_width=32, address_width=32, addressing="word")
+        self.dbus         = wishbone.Interface(data_width=32, address_width=32, addressing="word")
         self.periph_buses = [self.ibus, self.dbus]
         self.memory_buses = []
         self.interrupt    = Signal(15)
@@ -458,7 +458,7 @@ def __init__(self, platform, variant="standard"):
 
     def add_debug_module(self, dm):
         self.cpu_params.update(i_debug_req_i=dm.debug_req)
-        self.cpu_params.update(i_rst_ni=~(ResetSignal() | dm.ndmreset))
+        self.cpu_params.update(i_rst_ni=~(ResetSignal("sys") | dm.ndmreset))
 
     def add_trace_core(self, trace):
         trace_if = trace.trace_if

litex/soc/cores/cpu/cv32e41p/core.py

@@ -183,8 +183,8 @@ def __init__(self, pads=None):
         if pads is None:
             pads = Record(self.jtag_layout)
         self.pads = pads
-        self.dmbus = wishbone.Interface()
-        self.sbbus = wishbone.Interface()
+        self.dmbus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
+        self.sbbus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
         dmbus = Record(obi_layout)
         sbbus = Record(obi_layout)
 
@@ -267,8 +267,8 @@ def __init__(self, platform, variant="standard"):
         self.platform          = platform
         self.variant           = variant
         self.reset             = Signal()
-        self.ibus              = wishbone.Interface()
-        self.dbus              = wishbone.Interface()
+        self.ibus              = wishbone.Interface(data_width=32, address_width=32, addressing="word")
+        self.dbus              = wishbone.Interface(data_width=32, address_width=32, addressing="word")
         self.periph_buses      = [self.ibus, self.dbus]
         self.memory_buses      = []
         self.interrupt         = Signal(16)
@@ -321,7 +321,7 @@ def __init__(self, platform, variant="standard"):
             i_apu_rvalid_i = 0,
 
             # IRQ.
-            i_irq_i          = Cat(self.interrupt_padding,self.interrupt),
+            i_irq_i          = Cat(self.interrupt_padding, self.interrupt),
 
             # Debug.
             i_debug_req_i    = 0,
@@ -335,7 +335,7 @@ def __init__(self, platform, variant="standard"):
 
     def add_debug_module(self, dm):
         self.cpu_params.update(i_debug_req_i=dm.debug_req)
-        self.cpu_params.update(i_rst_ni=~(ResetSignal() | dm.ndmreset))
+        self.cpu_params.update(i_rst_ni=~(ResetSignal("sys") | dm.ndmreset))
 
     def set_reset_address(self, reset_address):
         self.reset_address = reset_address

litex/soc/cores/cpu/cva5/core.py

@@ -85,8 +85,8 @@ def __init__(self, platform, variant="standard"):
         if variant == "minimal":
             # Minimal variant has no caches, no multiply or divide support, and no branch predictor.
             # It also uses separate fetch and load-store wishbone interfaces.
-            self.ibus = ibus = wishbone.Interface()
-            self.dbus = dbus = wishbone.Interface()
+            self.ibus = ibus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
+            self.dbus = dbus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
             self.periph_buses.append(ibus)
             self.periph_buses.append(dbus)
             self.cpu_params.update(
@@ -117,7 +117,7 @@ def __init__(self, platform, variant="standard"):
         if variant == "standard":
             # Standard variant includes instruction and data caches, multiply and divide support
             # along with the branch predictor. It uses a shared wishbone interface.
-            self.idbus = idbus = wishbone.Interface()
+            self.idbus = idbus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
             self.periph_buses.append(idbus)
             self.cpu_params.update(
                 o_idbus_adr   = idbus.adr,

litex/soc/cores/cpu/eos_s3/core.py

@@ -47,7 +47,7 @@ def __init__(self, platform, variant, *args, **kwargs):
         self.platform       = platform
         self.reset          = Signal()
         self.interrupt      = Signal(4)
-        self.pbus           = wishbone.Interface(data_width=32, adr_width=15)
+        self.pbus           = wishbone.Interface(data_width=32, adr_width=15, addressing="byte")
         self.periph_buses   = [self.pbus]
         self.memory_buses   = []
 
@@ -84,7 +84,7 @@ def __init__(self, platform, variant, *args, **kwargs):
             # -----------
             i_WB_CLK       = ClockSignal("eos_s3_0"),
             o_WB_RST       = pbus_rst,
-            o_WBs_ADR      = Cat(Signal(2), self.pbus.adr),
+            o_WBs_ADR      = self.pbus.adr,
             o_WBs_CYC      = self.pbus.cyc,
             o_WBs_BYTE_STB = self.pbus.sel,
             o_WBs_WE       = self.pbus.we,

litex/soc/cores/cpu/femtorv/core.py

@@ -71,7 +71,7 @@ def __init__(self, platform, variant="standard"):
         self.variant      = variant
         self.human_name   = f"FemtoRV-{variant.upper()}"
         self.reset        = Signal()
-        self.idbus        = idbus = wishbone.Interface()
+        self.idbus        = idbus = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
         self.periph_buses = [idbus] # Peripheral buses (Connected to main SoC's bus).
         self.memory_buses = []      # Memory buses (Connected directly to LiteDRAM).
 
@@ -119,7 +119,7 @@ def __init__(self, platform, variant="standard"):
         self.fsm = fsm = FSM(reset_state="WAIT")
         fsm.act("WAIT",
             # Latch Address + Bytes to Words conversion.
-            NextValue(idbus.adr, mbus.addr[2:]),
+            NextValue(idbus.adr, mbus.addr),
 
             # Latch Wdata/WMask.
             NextValue(idbus.dat_w, mbus.wdata),

litex/soc/cores/cpu/firev/core.py

@@ -59,7 +59,7 @@ def __init__(self, platform, variant="standard"):
         self.variant      = variant
         self.human_name   = f"FireV-{variant.upper()}"
         self.reset        = Signal()
-        self.idbus        = idbus = wishbone.Interface()
+        self.idbus        = idbus = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
         self.periph_buses = [idbus] # Peripheral buses (Connected to main SoC's bus).
         self.memory_buses = []      # Memory buses (Connected directly to LiteDRAM).
 
@@ -115,7 +115,7 @@ def __init__(self, platform, variant="standard"):
         )
         self.comb += [
             idbus.we.eq(mbus.out_ram_rw),
-            idbus.adr.eq(mbus.out_ram_addr[2:]),
+            idbus.adr.eq(mbus.out_ram_addr),
             idbus.sel.eq(mbus.out_ram_wmask),
             idbus.dat_w.eq(mbus.out_ram_data_in),
 

litex/soc/cores/cpu/gowin_emcu/core.py

@@ -168,7 +168,7 @@ def __init__(self, platform, variant, *args, **kwargs):
 
         # Extension AHB -> Wishbone CSR via bridge
 
-        self.pbus = wishbone.Interface(data_width=32, adr_width=30)
+        self.pbus = wishbone.Interface(data_width=32, adr_width=30, addressing="word")
         self.periph_buses = [self.pbus]
         ahb_targexp0 = ahb.Interface()
         for s, _ in ahb_targexp0.master_signals:

litex/soc/cores/cpu/ibex/core.py

@@ -57,7 +57,7 @@ def __init__(self, obi, wb):
             # On OBI request:
             If(obi.req,
                 # Drive Wishbone bus from OBI bus.
-                wb.adr.eq(obi.addr[2:32]),
+                wb.adr.eq(     obi.addr),
                 wb.stb.eq(            1),
                 wb.dat_w.eq(  obi.wdata),
                 wb.cyc.eq(            1),
@@ -77,7 +77,7 @@ def __init__(self, obi, wb):
         )
         fsm.act("ACK",
             # Drive Wishbone bus from stored OBI bus values.
-            wb.adr.eq(addr[2:32]),
+            wb.adr.eq(      addr),
             wb.stb.eq(         1),
             wb.dat_w.eq(   wdata),
             wb.cyc.eq(         1),
@@ -121,8 +121,8 @@ def __init__(self, platform, variant="standard"):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
-        self.ibus         = wishbone.Interface()
-        self.dbus         = wishbone.Interface()
+        self.ibus         = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
+        self.dbus         = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
         self.periph_buses = [self.ibus, self.dbus]
         self.memory_buses = []
         self.interrupt    = Signal(15)

litex/soc/cores/cpu/lm32/core.py

@@ -51,8 +51,8 @@ def __init__(self, platform, variant="standard"):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
-        self.ibus         = ibus = wishbone.Interface()
-        self.dbus         = dbus = wishbone.Interface()
+        self.ibus         = ibus = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
+        self.dbus         = dbus = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
         self.interrupt    = Signal(32)
         self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus).
         self.memory_buses = []           # Memory buses (Connected directly to LiteDRAM).
@@ -68,7 +68,7 @@ def __init__(self, platform, variant="standard"):
             i_interrupt=self.interrupt,
 
             # IBus.
-            o_I_ADR_O = Cat(Signal(2), ibus.adr),
+            o_I_ADR_O = ibus.adr,
             o_I_DAT_O = ibus.dat_w,
             o_I_SEL_O = ibus.sel,
             o_I_CYC_O = ibus.cyc,
@@ -82,7 +82,7 @@ def __init__(self, platform, variant="standard"):
             i_I_RTY_I = 0,
 
             # DBus.
-            o_D_ADR_O = Cat(Signal(2), dbus.adr),
+            o_D_ADR_O = dbus.adr,
             o_D_DAT_O = dbus.dat_w,
             o_D_SEL_O = dbus.sel,
             o_D_CYC_O = dbus.cyc,

litex/soc/cores/cpu/marocchino/core.py

@@ -84,8 +84,8 @@ def __init__(self, platform, variant="standard"):
         self.variant      = variant
         self.reset        = Signal()
         self.interrupt    = Signal(32)
-        self.ibus         = ibus = wishbone.Interface()
-        self.dbus         = dbus = wishbone.Interface()
+        self.ibus         = ibus = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
+        self.dbus         = dbus = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
         self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus).
         self.memory_buses = []           # Memory buses (Connected directly to LiteDRAM).
 
@@ -117,13 +117,13 @@ def __init__(self, platform, variant="standard"):
             **cpu_args,
 
             # Clk / Rst.
-            i_wb_clk = ClockSignal("sys"),
-            i_wb_rst = ResetSignal("sys") | self.reset,
+            i_wb_clk  = ClockSignal("sys"),
+            i_wb_rst  = ResetSignal("sys") | self.reset,
             i_cpu_clk = ClockSignal("sys"),
             i_cpu_rst = ResetSignal("sys") | self.reset,
 
             # IBus.
-            o_iwbm_adr_o = Cat(Signal(2), ibus.adr),
+            o_iwbm_adr_o = ibus.adr,
             o_iwbm_stb_o = ibus.stb,
             o_iwbm_cyc_o = ibus.cyc,
             o_iwbm_sel_o = ibus.sel,
@@ -137,7 +137,7 @@ def __init__(self, platform, variant="standard"):
             i_iwbm_rty_i = 0,
 
             # DBus.
-            o_dwbm_adr_o = Cat(Signal(2), dbus.adr),
+            o_dwbm_adr_o = dbus.adr,
             o_dwbm_stb_o = dbus.stb,
             o_dwbm_cyc_o = dbus.cyc,
             o_dwbm_sel_o = dbus.sel,

litex/soc/cores/cpu/microwatt/core.py

@@ -71,8 +71,8 @@ def __init__(self, platform, variant="standard"):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
-        self.ibus         = ibus = wishbone.Interface(data_width=64, adr_width=29)
-        self.dbus         = dbus = wishbone.Interface(data_width=64, adr_width=29)
+        self.ibus         = ibus = wishbone.Interface(data_width=64, adr_width=29, addressing="word")
+        self.dbus         = dbus = wishbone.Interface(data_width=64, adr_width=29, addressing="word")
         self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus).
         self.memory_buses = []           # Memory buses (Connected directly to LiteDRAM).
         if "irq" in variant:
@@ -240,8 +240,8 @@ class XICSSlave(Module, AutoCSR):
     def __init__(self, platform, core_irq_out=Signal(), int_level_in=Signal(16), variant="standard"):
         self.variant = variant
 
-        self.icp_bus = icp_bus = wishbone.Interface(data_width=32, adr_width=12)
-        self.ics_bus = ics_bus = wishbone.Interface(data_width=32, adr_width=12)
+        self.icp_bus = icp_bus = wishbone.Interface(data_width=32, adr_width=12, addressing="word")
+        self.ics_bus = ics_bus = wishbone.Interface(data_width=32, adr_width=12, addressing="word")
 
         # XICS Signals.
         self.ics_icp_xfer_src = Signal(4)

litex/soc/cores/cpu/minerva/core.py

@@ -48,8 +48,8 @@ def __init__(self, platform, variant="standard"):
         self.variant      = variant
         self.reset        = Signal()
         self.interrupt    = Signal(32)
-        self.ibus         = ibus = wishbone.Interface()
-        self.dbus         = dbus = wishbone.Interface()
+        self.ibus         = ibus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
+        self.dbus         = dbus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
         self.periph_buses = [self.ibus, self.dbus] # Peripheral buses (Connected to main SoC's bus).
         self.memory_buses = []                     # Memory buses (Connected directly to LiteDRAM).
 

litex/soc/cores/cpu/mor1kx/core.py

@@ -84,8 +84,8 @@ def __init__(self, platform, variant="standard"):
         self.variant      = variant
         self.reset        = Signal()
         self.interrupt    = Signal(32)
-        self.ibus         = ibus = wishbone.Interface()
-        self.dbus         = dbus = wishbone.Interface()
+        self.ibus         = ibus = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
+        self.dbus         = dbus = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
         self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus).
         self.memory_buses = []           # Memory buses (Connected directly to LiteDRAM).
 
@@ -160,7 +160,7 @@ def __init__(self, platform, variant="standard"):
             i_irq_i=self.interrupt,
 
             # IBus.
-            o_iwbm_adr_o = Cat(Signal(2), ibus.adr),
+            o_iwbm_adr_o = ibus.adr,
             o_iwbm_dat_o = ibus.dat_w,
             o_iwbm_sel_o = ibus.sel,
             o_iwbm_cyc_o = ibus.cyc,
@@ -174,7 +174,7 @@ def __init__(self, platform, variant="standard"):
             i_iwbm_rty_i = 0,
 
             # DBus.
-            o_dwbm_adr_o = Cat(Signal(2), dbus.adr),
+            o_dwbm_adr_o = dbus.adr,
             o_dwbm_dat_o = dbus.dat_w,
             o_dwbm_sel_o = dbus.sel,
             o_dwbm_cyc_o = dbus.cyc,

litex/soc/cores/cpu/neorv32/core.py

@@ -75,7 +75,7 @@ def __init__(self, platform, variant="standard"):
         self.variant      = variant
         self.human_name   = f"NEORV32-{variant}"
         self.reset        = Signal()
-        self.ibus         = idbus = wishbone.Interface()
+        self.ibus         = idbus = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
         self.periph_buses = [idbus] # Peripheral buses (Connected to main SoC's bus).
         self.memory_buses = []      # Memory buses (Connected directly to LiteDRAM).
 
@@ -98,7 +98,7 @@ def __init__(self, platform, variant="standard"):
             i_mext_irq_i  = 0,
 
             # I/D Wishbone Bus.
-            o_wb_adr_o = Cat(Signal(2), idbus.adr),
+            o_wb_adr_o = idbus.adr,
             i_wb_dat_i = idbus.dat_r,
             o_wb_dat_o = idbus.dat_w,
             o_wb_we_o  = idbus.we,