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Fix minstret csr
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In past, minstret csr use bubble to judge if there is a valid inst
retired. However, this may cause branch inst not be counted because
branch inst also raise bubble to 1.
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@fennecJ
fennecJ committed Oct 27, 2024
1 parent a452c6e commit bb62f08
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Showing 5 changed files with 47 additions and 9 deletions.
28 changes: 24 additions & 4 deletions RV12/rtl/verilog/core/ex/riscv_bu.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -60,6 +60,7 @@ import riscv_state_pkg::*;
bu_bp_history_o,
output reg bu_bp_btaken_o,
output reg bu_bp_update_o,
output reg bu_bubble_o,

//Instruction
input instruction_t id_insn_i,
Expand Down Expand Up @@ -104,13 +105,20 @@ import riscv_state_pkg::*;
bp_update;
logic [BP_GLOBAL_BITS:0] bp_history;
logic [XLEN -1:0] nxt_pc;


logic bu_bubble;
////////////////////////////////////////////////////////////////
//
// Module Body
//

// For inst retired
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni ) bu_bubble_o <= 1'b1;
else if ( ex_exceptions_i.any ||
mem_exceptions_i.any ||
wb_exceptions_i.any ) bu_bubble_o <= 1'b1;
else if (!ex_stall_i ) bu_bubble_o <= bu_bubble;

/*
* Instruction
*/
Expand Down Expand Up @@ -175,6 +183,7 @@ import riscv_state_pkg::*;
dc_invalidate = 'b0;
dc_clean = 'b0;
nxt_pc = id_pc_i + ext_immUJ;
bu_bubble = 1'b0;
end
{1'b0,JALR }: if (has_rsb)
begin
Expand All @@ -186,6 +195,7 @@ import riscv_state_pkg::*;
dc_clean = 'b0;

nxt_pc = (opA_i + opB_i) & { {XLEN-1{1'b1}},1'b0 };
bu_bubble = 1'b0;
pipeflush = is_ret ? (nxt_pc[XLEN-1:1] != id_rsb_pc_i[XLEN-1:1]) : 1'b1;
end
else
Expand All @@ -198,6 +208,7 @@ import riscv_state_pkg::*;
dc_invalidate = 'b0;
dc_clean = 'b0;
nxt_pc = (opA_i + opB_i) & { {XLEN-1{1'b1}},1'b0 };
bu_bubble = 1'b0;
end
{1'b0,BEQ }: begin
btaken = (opA_i == opB_i);
Expand All @@ -208,6 +219,7 @@ import riscv_state_pkg::*;
dc_invalidate = 'b0;
dc_clean = 'b0;
nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i +(is_16bit_instruction ? 'h2 : 'h4);
bu_bubble = 1'b0;
end
{1'b0,BNE }: begin
btaken = (opA_i != opB_i);
Expand All @@ -218,6 +230,7 @@ import riscv_state_pkg::*;
dc_invalidate = 'b0;
dc_clean = 'b0;
nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i + (is_16bit_instruction ? 'h2 : 'h4);
bu_bubble = 1'b0;
end
{1'b0,BLTU }: begin
btaken = (opA_i < opB_i);
Expand All @@ -228,6 +241,7 @@ import riscv_state_pkg::*;
dc_invalidate = 'b0;
dc_clean = 'b0;
nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i + 'h4;
bu_bubble = 1'b0;
end
{1'b0,BGEU }: begin
btaken = (opA_i >= opB_i);
Expand All @@ -238,6 +252,7 @@ import riscv_state_pkg::*;
dc_invalidate = 'b0;
dc_clean = 'b0;
nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i +'h4;
bu_bubble = 1'b0;
end
{1'b0,BLT }: begin
btaken = $signed(opA_i) < $signed(opB_i);
Expand All @@ -248,6 +263,7 @@ import riscv_state_pkg::*;
dc_invalidate = 'b0;
dc_clean = 'b0;
nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i + 'h4;
bu_bubble = 1'b0;
end
{1'b0,BGE }: begin
btaken = $signed(opA_i) >= $signed(opB_i);
Expand All @@ -258,6 +274,7 @@ import riscv_state_pkg::*;
dc_invalidate = 'b0;
dc_clean = 'b0;
nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i + 'h4;
bu_bubble = 1'b0;
end
{1'b0,MISCMEM}: case (id_insn_i.instr)
FENCE_I: begin
Expand All @@ -269,7 +286,8 @@ import riscv_state_pkg::*;
dc_invalidate = 'b0;
dc_clean = 'b1;
nxt_pc = id_pc_i +'h4;
end
bu_bubble = 1'b0;
end
default: begin
btaken = 'b0;
bp_update = 'b0;
Expand All @@ -279,7 +297,8 @@ import riscv_state_pkg::*;
dc_invalidate = 'b0;
dc_clean = 'b0;
nxt_pc = id_pc_i + 'h4;
end
bu_bubble = 1'b1;
end
endcase
default : begin
btaken = 'b0;
Expand All @@ -290,6 +309,7 @@ import riscv_state_pkg::*;
dc_invalidate = 'b0;
dc_clean = 'b0;
nxt_pc = id_pc_i + (is_16bit_instruction ? 'h2 : 'h4);
bu_bubble = 1'b1;
end
endcase

Expand Down
6 changes: 4 additions & 2 deletions RV12/rtl/verilog/core/riscv_ex.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -131,6 +131,7 @@ import biu_constants_pkg::*;
logic alu_bubble,
lsu_bubble,
mul_bubble,
bu_bubble,
div_bubble;

//Pipeline stalls
Expand All @@ -146,7 +147,7 @@ import biu_constants_pkg::*;
////////////////////////////////////////////////////////////////
//
// Module Body
//
//

/*
* Program Counter
Expand Down Expand Up @@ -293,7 +294,7 @@ import biu_constants_pkg::*;
.mem_exceptions_i ( mem_exceptions_i ),
.wb_exceptions_i ( wb_exceptions_i ),
.bu_exceptions_o ( ex_exceptions_o ),

.bu_bubble_o (bu_bubble),
.opA_i ( opA ),
.opB_i ( opB ) );

Expand Down Expand Up @@ -361,6 +362,7 @@ endgenerate
*/

assign ex_insn_o.bubble = alu_bubble & lsu_bubble & mul_bubble & div_bubble;
assign ex_insn_o.retired = ~(alu_bubble & lsu_bubble & bu_bubble & mul_bubble & div_bubble);
assign ex_stall_o = mem_stall_i | lsu_stall | mul_stall | div_stall;

//result
Expand Down
9 changes: 8 additions & 1 deletion RV12/rtl/verilog/core/riscv_mem.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@
// See the License for permissions and limitations under the //
// License. //
// //
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////


module riscv_mem
Expand Down Expand Up @@ -69,6 +69,13 @@ import riscv_state_pkg::*;
// Module Body
//

// inst retired

always @(posedge clk_i, negedge rst_ni)
if (!rst_ni ) mem_insn_o.retired <= 'h0;
else if ( mem_exceptions_up_i.any) mem_insn_o.retired <= 'h0;
else if (!mem_stall_i ) mem_insn_o.retired <= mem_insn_i.retired;

/*
* Program Counter
*/
Expand Down
6 changes: 4 additions & 2 deletions RV12/rtl/verilog/core/riscv_state1.10.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -797,8 +797,10 @@ generate
else if ( (ex_csr_we_i && ex_csr_reg_i == MINSTRETH && st_prv_o == PRV_M) ||
(du_we_csr_i && du_addr_i == MINSTRETH) )
csr.minstret.h <= csr_wval;
else if (!wb_insn_i.bubble)
csr.minstret <= csr.minstret + 'h1;
else
csr.minstret <= csr.minstret + wb_insn_i.retired;
// else if (!wb_insn_i.bubble)
// csr.minstret <= csr.minstret + 'h1;
end
end
else //(XLEN > 32)
Expand Down
7 changes: 7 additions & 0 deletions RV12/rtl/verilog/core/riscv_wb.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -95,6 +95,13 @@ import riscv_state_pkg::*;
// Module Body
//


always @(posedge clk_i, negedge rst_ni)
if (!rst_ni ) wb_insn_o.retired <= 'h0;
else if ( wb_exceptions_o.any) wb_insn_o.retired <= 'h0;
else if ( wb_stall_o ) wb_insn_o.retired <= 'h0;
else wb_insn_o.retired <= mem_insn_i.retired;

/*
* Program Counter
*/
Expand Down

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