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fix nano sdram initialization
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@nand2mario
nand2mario committed Apr 7, 2024
1 parent 895d4fa commit 1c00dc5
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Showing 3 changed files with 204 additions and 26 deletions.
194 changes: 186 additions & 8 deletions src/nes.gao
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
<GAO_CONFIG>
<Version>3.0</Version>
<Mode>Standard</Mode>
<AoCore index="0" sample_clock="fclk" trig_type="0" storage_depth="2048" window_num="1" capture_amount="2048" implementation="0" trigger_pos="0" module_name="nestang_top" force_trigger_by_falling_edge="false">
<AoCore index="0" sample_clock="fclk" trig_type="0" storage_depth="1024" window_num="1" capture_amount="1024" implementation="0" trigger_pos="0" module_name="nestang_top" force_trigger_by_falling_edge="false">
<SignalList>
<Signal capture_enable="true">clk</Signal>
<Signal capture_enable="true">loading</Signal>
Expand Down Expand Up @@ -136,7 +136,6 @@
<Signal>sdram/cycle[1]</Signal>
<Signal>sdram/cycle[0]</Signal>
</Bus>
<Signal capture_enable="true">sdram/oeB</Signal>
<Signal capture_enable="true">nes/prg_allow</Signal>
<Signal capture_enable="true">nes/prg_read</Signal>
<Bus capture_enable="true" name="loader/ines[4][7:0]">
Expand All @@ -159,6 +158,177 @@
<Signal>loader/ines[5][1]</Signal>
<Signal>loader/ines[5][0]</Signal>
</Bus>
<Bus capture_enable="true" name="rv_addr_Z[9:2]">
<Signal>rv_addr_Z[9]</Signal>
<Signal>rv_addr_Z[8]</Signal>
<Signal>rv_addr_Z[7]</Signal>
<Signal>rv_addr_Z[6]</Signal>
<Signal>rv_addr_Z[5]</Signal>
<Signal>rv_addr_Z[4]</Signal>
<Signal>rv_addr_Z[3]</Signal>
<Signal>rv_addr_Z[2]</Signal>
</Bus>
<Signal capture_enable="true">rv_valid_Z</Signal>
<Bus capture_enable="true" name="flash_wstrb[3:0]">
<Signal>flash_wstrb[3]</Signal>
<Signal>flash_wstrb[2]</Signal>
<Signal>flash_wstrb[1]</Signal>
<Signal>flash_wstrb[0]</Signal>
</Bus>
<Bus capture_enable="true" name="rv_dout_Z[15:0]">
<Signal>rv_dout_Z[15]</Signal>
<Signal>rv_dout_Z[14]</Signal>
<Signal>rv_dout_Z[13]</Signal>
<Signal>rv_dout_Z[12]</Signal>
<Signal>rv_dout_Z[11]</Signal>
<Signal>rv_dout_Z[10]</Signal>
<Signal>rv_dout_Z[9]</Signal>
<Signal>rv_dout_Z[8]</Signal>
<Signal>rv_dout_Z[7]</Signal>
<Signal>rv_dout_Z[6]</Signal>
<Signal>rv_dout_Z[5]</Signal>
<Signal>rv_dout_Z[4]</Signal>
<Signal>rv_dout_Z[3]</Signal>
<Signal>rv_dout_Z[2]</Signal>
<Signal>rv_dout_Z[1]</Signal>
<Signal>rv_dout_Z[0]</Signal>
</Bus>
<Bus capture_enable="true" name="rv_wdata_Z[15:0]">
<Signal>rv_wdata_Z[15]</Signal>
<Signal>rv_wdata_Z[14]</Signal>
<Signal>rv_wdata_Z[13]</Signal>
<Signal>rv_wdata_Z[12]</Signal>
<Signal>rv_wdata_Z[11]</Signal>
<Signal>rv_wdata_Z[10]</Signal>
<Signal>rv_wdata_Z[9]</Signal>
<Signal>rv_wdata_Z[8]</Signal>
<Signal>rv_wdata_Z[7]</Signal>
<Signal>rv_wdata_Z[6]</Signal>
<Signal>rv_wdata_Z[5]</Signal>
<Signal>rv_wdata_Z[4]</Signal>
<Signal>rv_wdata_Z[3]</Signal>
<Signal>rv_wdata_Z[2]</Signal>
<Signal>rv_wdata_Z[1]</Signal>
<Signal>rv_wdata_Z[0]</Signal>
</Bus>
<Signal capture_enable="true">rv_req</Signal>
<Signal capture_enable="true">rv_req_ack_Z</Signal>
<Bus capture_enable="true" name="rv_ds[1:0]">
<Signal>rv_ds[1]</Signal>
<Signal>rv_ds[0]</Signal>
</Bus>
<Signal capture_enable="true">rv_word</Signal>
<Bus capture_enable="true" name="CMD" restorename="group_0[3:0]">
<Signal>O_sdram_cs_n</Signal>
<Signal>O_sdram_ras_n</Signal>
<Signal>O_sdram_cas_n</Signal>
<Signal>O_sdram_wen_n</Signal>
</Bus>
<Bus capture_enable="true" name="O_sdram_addr[10:0]">
<Signal>O_sdram_addr[10]</Signal>
<Signal>O_sdram_addr[9]</Signal>
<Signal>O_sdram_addr[8]</Signal>
<Signal>O_sdram_addr[7]</Signal>
<Signal>O_sdram_addr[6]</Signal>
<Signal>O_sdram_addr[5]</Signal>
<Signal>O_sdram_addr[4]</Signal>
<Signal>O_sdram_addr[3]</Signal>
<Signal>O_sdram_addr[2]</Signal>
<Signal>O_sdram_addr[1]</Signal>
<Signal>O_sdram_addr[0]</Signal>
</Bus>
<Bus capture_enable="true" name="IO_sdram_dq[31:0]">
<Signal>IO_sdram_dq[31]</Signal>
<Signal>IO_sdram_dq[30]</Signal>
<Signal>IO_sdram_dq[29]</Signal>
<Signal>IO_sdram_dq[28]</Signal>
<Signal>IO_sdram_dq[27]</Signal>
<Signal>IO_sdram_dq[26]</Signal>
<Signal>IO_sdram_dq[25]</Signal>
<Signal>IO_sdram_dq[24]</Signal>
<Signal>IO_sdram_dq[23]</Signal>
<Signal>IO_sdram_dq[22]</Signal>
<Signal>IO_sdram_dq[21]</Signal>
<Signal>IO_sdram_dq[20]</Signal>
<Signal>IO_sdram_dq[19]</Signal>
<Signal>IO_sdram_dq[18]</Signal>
<Signal>IO_sdram_dq[17]</Signal>
<Signal>IO_sdram_dq[16]</Signal>
<Signal>IO_sdram_dq[15]</Signal>
<Signal>IO_sdram_dq[14]</Signal>
<Signal>IO_sdram_dq[13]</Signal>
<Signal>IO_sdram_dq[12]</Signal>
<Signal>IO_sdram_dq[11]</Signal>
<Signal>IO_sdram_dq[10]</Signal>
<Signal>IO_sdram_dq[9]</Signal>
<Signal>IO_sdram_dq[8]</Signal>
<Signal>IO_sdram_dq[7]</Signal>
<Signal>IO_sdram_dq[6]</Signal>
<Signal>IO_sdram_dq[5]</Signal>
<Signal>IO_sdram_dq[4]</Signal>
<Signal>IO_sdram_dq[3]</Signal>
<Signal>IO_sdram_dq[2]</Signal>
<Signal>IO_sdram_dq[1]</Signal>
<Signal>IO_sdram_dq[0]</Signal>
</Bus>
<Bus capture_enable="true" name="O_sdram_ba[1:0]">
<Signal>O_sdram_ba[1]</Signal>
<Signal>O_sdram_ba[0]</Signal>
</Bus>
<Bus capture_enable="true" name="O_sdram_dqm[3:0]">
<Signal>O_sdram_dqm[3]</Signal>
<Signal>O_sdram_dqm[2]</Signal>
<Signal>O_sdram_dqm[1]</Signal>
<Signal>O_sdram_dqm[0]</Signal>
</Bus>
<Signal capture_enable="false">sdram/oeB</Signal>
<Bus capture_enable="false" name="O_sdram_addr_d[10:0]">
<Signal>O_sdram_addr_d[10]</Signal>
<Signal>O_sdram_addr_d[9]</Signal>
<Signal>O_sdram_addr_d[8]</Signal>
<Signal>O_sdram_addr_d[7]</Signal>
<Signal>O_sdram_addr_d[6]</Signal>
<Signal>O_sdram_addr_d[5]</Signal>
<Signal>O_sdram_addr_d[4]</Signal>
<Signal>O_sdram_addr_d[3]</Signal>
<Signal>O_sdram_addr_d[2]</Signal>
<Signal>O_sdram_addr_d[1]</Signal>
<Signal>O_sdram_addr_d[0]</Signal>
</Bus>
<Bus capture_enable="false" name="IO_sdram_dq_in[31:0]">
<Signal>IO_sdram_dq_in[31]</Signal>
<Signal>IO_sdram_dq_in[30]</Signal>
<Signal>IO_sdram_dq_in[29]</Signal>
<Signal>IO_sdram_dq_in[28]</Signal>
<Signal>IO_sdram_dq_in[27]</Signal>
<Signal>IO_sdram_dq_in[26]</Signal>
<Signal>IO_sdram_dq_in[25]</Signal>
<Signal>IO_sdram_dq_in[24]</Signal>
<Signal>IO_sdram_dq_in[23]</Signal>
<Signal>IO_sdram_dq_in[22]</Signal>
<Signal>IO_sdram_dq_in[21]</Signal>
<Signal>IO_sdram_dq_in[20]</Signal>
<Signal>IO_sdram_dq_in[19]</Signal>
<Signal>IO_sdram_dq_in[18]</Signal>
<Signal>IO_sdram_dq_in[17]</Signal>
<Signal>IO_sdram_dq_in[16]</Signal>
<Signal>IO_sdram_dq_in[15]</Signal>
<Signal>IO_sdram_dq_in[14]</Signal>
<Signal>IO_sdram_dq_in[13]</Signal>
<Signal>IO_sdram_dq_in[12]</Signal>
<Signal>IO_sdram_dq_in[11]</Signal>
<Signal>IO_sdram_dq_in[10]</Signal>
<Signal>IO_sdram_dq_in[9]</Signal>
<Signal>IO_sdram_dq_in[8]</Signal>
<Signal>IO_sdram_dq_in[7]</Signal>
<Signal>IO_sdram_dq_in[6]</Signal>
<Signal>IO_sdram_dq_in[5]</Signal>
<Signal>IO_sdram_dq_in[4]</Signal>
<Signal>IO_sdram_dq_in[3]</Signal>
<Signal>IO_sdram_dq_in[2]</Signal>
<Signal>IO_sdram_dq_in[1]</Signal>
<Signal>IO_sdram_dq_in[0]</Signal>
</Bus>
</SignalList>
<Triggers>
<Trigger index="0">
Expand All @@ -172,8 +342,16 @@
<Signal>loading_r</Signal>
</SignalList>
</Trigger>
<Trigger index="2"/>
<Trigger index="3"/>
<Trigger index="2">
<SignalList>
<Signal>rv_valid_Z</Signal>
</SignalList>
</Trigger>
<Trigger index="3">
<SignalList>
<Signal>iosys/flash_loaded</Signal>
</SignalList>
</Trigger>
<Trigger index="4"/>
<Trigger index="5"/>
<Trigger index="6"/>
Expand All @@ -190,8 +368,8 @@
<MatchUnits>
<MatchUnit index="0" enabled="1" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="1" value1="0" trigger="0"/>
<MatchUnit index="1" enabled="1" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="01" value1="00" trigger="1"/>
<MatchUnit index="2" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
<MatchUnit index="3" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
<MatchUnit index="2" enabled="1" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="1" value1="0" trigger="2"/>
<MatchUnit index="3" enabled="1" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="1" value1="0" trigger="3"/>
<MatchUnit index="4" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
<MatchUnit index="5" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
<MatchUnit index="6" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
Expand All @@ -206,8 +384,8 @@
<MatchUnit index="15" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
</MatchUnits>
<Expressions type="Static">
<Expression>M1</Expression>
<Expression>M2</Expression>
</Expressions>
</AoCore>
<GAO_ID>1111101111011101</GAO_ID>
<GAO_ID>0011100010011110</GAO_ID>
</GAO_CONFIG>
1 change: 1 addition & 0 deletions src/nestang_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -194,6 +194,7 @@ reg [7:0] reset_cnt = 255; // reset for 255 cycles before start everything
always @(posedge clk) begin
reset_cnt <= reset_cnt == 0 ? 0 : reset_cnt - 1;
if (reset_cnt == 0)
// if (reset_cnt == 0 && s1) // for nano
sys_resetn <= ~(nes_btn[5] && nes_btn[2]); // 8BitDo Home button = Select + Down
end

Expand Down
35 changes: 17 additions & 18 deletions src/sdram_nes.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -20,15 +20,12 @@ module sdram_nes #(
// Clock frequency, max 66.7Mhz with current set of T_xx/CAS parameters.
parameter FREQ = 64_800_000,

// Time delays for 66.7Mhz max clock (min clock cycle 15ns)
// The SDRAM supports max 166.7Mhz (RP/RCD/RC need changes)
// Alliance AS4C32M16SB-7TIN 512Mb
parameter [3:0] CAS = 4'd2, // 2/3 cycles, set in mode register
parameter [3:0] T_WR = 4'd2, // 2 cycles, write recovery
parameter [3:0] T_MRD= 4'd2, // 2 cycles, mode register set
parameter [3:0] T_RP = 4'd1, // 15ns, precharge to active
parameter [3:0] T_RCD= 4'd1, // 15ns, active to r/w
parameter [3:0] T_RC = 4'd4 // 63ns, ref/active to ref/active
parameter [4:0] CAS = 4'd2, // 2/3 cycles, set in mode register
parameter [4:0] T_WR = 4'd2, // 2 cycles, write recovery
parameter [4:0] T_MRD= 4'd2, // 2 cycles, mode register set
parameter [4:0] T_RP = 4'd2, // 15ns, precharge to active
parameter [4:0] T_RCD= 4'd2, // 15ns, active to r/w
parameter [4:0] T_RC = 4'd6 // 63ns, ref/active to ref/active
) (
inout reg [SDRAM_DATA_WIDTH-1:0] SDRAM_DQ, // 16 bit bidirectional data bus
output [SDRAM_ROW_WIDTH-1:0] SDRAM_A, // 13 bit multiplexed address bus
Expand Down Expand Up @@ -76,9 +73,9 @@ reg [SDRAM_DATA_WIDTH-1:0] dq_out;
assign SDRAM_DQ = dq_oen ? {SDRAM_DATA_WIDTH{1'bz}} : dq_out;
wire [SDRAM_DATA_WIDTH-1:0] dq_in = SDRAM_DQ; // DQ input
reg [3:0] cmd;
reg [12:0] a;
reg [SDRAM_ROW_WIDTH-1:0] a;
assign {SDRAM_nCS, SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} = cmd;
assign SDRAM_A = SDRAM_ROW_WIDTH'(a);
assign SDRAM_A = a;

assign SDRAM_CKE = 1'b1;

Expand All @@ -98,7 +95,7 @@ localparam [10:0] MODE_REG = {4'b0, CAS[2:0], BURST_MODE, BURST_LEN};
localparam RFRSH_CYCLES = 9'd501;

// state
reg [11:0] cycle; // one hot encoded
reg [16:0] cycle; // one hot encoded
reg normal, setup;
reg cfg_now; // pulse for configuration

Expand Down Expand Up @@ -208,27 +205,29 @@ always @(posedge clk) begin

// setup process
if (setup) begin
cycle <= {cycle[10:0], 1'b0}; // cycle 0-11 for setup
cycle <= {cycle[15:0], 1'b0}; // cycle 0-16 for setup
// configuration sequence
if (cycle[0]) begin
// precharge all
cmd <= CMD_PreCharge;
a[10] <= 1'b1;
SDRAM_BA <= 0;
end
if (cycle[T_RP]) begin
if (cycle[T_RP]) begin // 2
// 1st AutoRefresh
cmd <= CMD_AutoRefresh;
end
if (cycle[T_RP+T_RC]) begin
if (cycle[T_RP+T_RC]) begin // 8
// 2nd AutoRefresh
cmd <= CMD_AutoRefresh;
end
if (cycle[T_RP+T_RC+T_RC]) begin
if (cycle[T_RP+T_RC+T_RC]) begin // 14
// set register
cmd <= CMD_SetModeReg;
a[10:0] <= MODE_REG;
SDRAM_BA <= 0;
end
if (cycle[T_RP+T_RC+T_RC+T_MRD]) begin
if (cycle[T_RP+T_RC+T_RC+T_MRD]) begin // 16
setup <= 0;
normal <= 1;
cycle <= 1;
Expand All @@ -237,7 +236,7 @@ always @(posedge clk) begin
end
if (normal) begin
if (clkref & ~clkref_r) // go to cycle 5 after clkref posedge
cycle <= 12'b0000_0010_0000;
cycle[5:0] <= 6'b10_0000;
else
cycle[5:0] <= {cycle[4:0], cycle[5]};
refresh_cnt <= refresh_cnt + 1'd1;
Expand Down

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