fix nano hdmi clock

fjpolo · Apr 5, 2024 · a7f98a7 · a7f98a7
1 parent 7369532
commit a7f98a7
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Showing 3 changed files with 16 additions and 21 deletions.
diff --git a/nestang_nano20k.gprj b/nestang_nano20k.gprj
@@ -64,6 +64,7 @@
         <File path="src/tang_primer_25k/nestang.cst" type="file.cst" enable="0"/>
         <File path="src/tang_nano_20k/nestang.sdc" type="file.sdc" enable="1"/>
         <File path="src/tang_primer_25k/nestang.sdc" type="file.sdc" enable="0"/>
+        <File path="src/clock.gao" type="file.gao" enable="0"/>
         <File path="src/nes.gao" type="file.gao" enable="0"/>
     </FileList>
 </Project>
diff --git a/src/nes2hdmi.sv b/src/nes2hdmi.sv
@@ -23,7 +23,6 @@ module nes2hdmi (
 	// video clocks
 	input clk_pixel,
 	input clk_5x_pixel,
-	input locked,
 
     // output [7:0] led,
 
@@ -44,11 +43,11 @@ localparam SCALE = 5;
 localparam VIDEOID = 4;
 localparam VIDEO_REFRESH = 60.0;
 
-localparam IDIV_SEL_X5 = 3;
-localparam FBDIV_SEL_X5 = 54;
-localparam ODIV_SEL_X5 = 2;
-localparam DUTYDA_SEL_X5 = "1000";
-localparam DYN_SDIV_SEL_X5 = 2;
+// localparam IDIV_SEL_X5 = 3;
+// localparam FBDIV_SEL_X5 = 54;
+// localparam ODIV_SEL_X5 = 2;
+// localparam DUTYDA_SEL_X5 = "1000";
+// localparam DYN_SDIV_SEL_X5 = 2;
 
 localparam CLKFRQ = 74250;
 

diff --git a/src/nestang_top.sv b/src/nestang_top.sv
@@ -182,8 +182,12 @@ wire ext_audio;
 // Clocks
 ///////////////////////////
 
-wire clk, fclk, clk_sdram, clk27, clk_usb;
-assign O_sdram_clk = clk_sdram;
+wire clk;       // 21.477Mhz main clock
+wire fclk;      // 3x clk SDRAM clock
+wire hclk;      // 720p pixel clock: 74.25 Mhz
+wire hclk5;     // 5x pixel clock: 371.25 Mhz
+wire clk27;     // 27Mhz to generate hclk/hclk5
+wire clk_usb;   // 12Mhz USB clock
 
 reg sys_resetn = 0;
 reg [7:0] reset_cnt = 255;      // reset for 255 cycles before start everything
@@ -195,18 +199,14 @@ end
 
 `ifndef VERILATOR
 
-localparam FREQ = 21_477_000;
-
 `ifdef PRIMER
 // sysclk 50Mhz
 gowin_pll_27 pll_27 (.clkin(sys_clk), .clkout0(clk27));      // Primer25K: PLL to generate 27Mhz from 50Mhz
-
-gowin_pll_nes pll_nes (.clkin(sys_clk), .clkout0(clk), .clkout1(fclk), .clkout2(clk_sdram));
+gowin_pll_nes pll_nes (.clkin(sys_clk), .clkout0(clk), .clkout1(fclk), .clkout2(O_sdram_clk));
 `else
 // sys_clk 27Mhz
-wire clk27 = sys_clk;       // Nano20K: native 27Mhz system clock
-wire clk_sdram;  
-gowin_pll_nes pll_nes(.clkin(sys_clk), .clkoutd3(clk), .clkout(fclk), .clkoutp(clk_sdram));
+assign clk27 = sys_clk;       // Nano20K: native 27Mhz system clock
+gowin_pll_nes pll_nes(.clkin(sys_clk), .clkoutd3(clk), .clkout(fclk), .clkoutp(O_sdram_clk));
 `endif  // PRIMER
 
 // USB clock 12Mhz
@@ -215,10 +215,6 @@ gowin_pll_nes pll_nes(.clkin(sys_clk), .clkoutd3(clk), .clkout(fclk), .clkoutp(c
 //       .clkout(clk_usb)       // 12Mhz usb clock
 //   );
 
-// HDMI domain clocks
-wire hclk;     // 720p pixel clock: 74.25 Mhz
-wire hclk5;    // 5x pixel clock: 371.25 Mhz
-
 gowin_pll_hdmi pll_hdmi (
     .clkin(clk27),
     .clkout(hclk5)
@@ -236,7 +232,6 @@ CLKDIV #(.DIV_MODE(5)) div5 (
 // dummy clocks for verilator
 assign clk = sys_clk;
 assign fclk = sys_clk;
-assign clk_sdram = sys_clk;
 
 `endif  // verilator
 
@@ -370,7 +365,7 @@ nes2hdmi u_hdmi (     // purple: RGB=440064 (010001000_00000000_01100100), BGR5=
     .scanline(scanline), .sample(sample >> 1),
     .overlay(overlay), .overlay_x(overlay_x), .overlay_y(overlay_y),
     .overlay_color(overlay_color),
-    .clk_pixel(hclk), .clk_5x_pixel(hclk5), .locked(pll_lock),
+    .clk_pixel(hclk), .clk_5x_pixel(hclk5),
     .tmds_clk_n(tmds_clk_n), .tmds_clk_p(tmds_clk_p),
     .tmds_d_n(tmds_d_n), .tmds_d_p(tmds_d_p)
 );