Skip to content

Commit

Permalink
fix verilator memory access. helloworld and
Browse files Browse the repository at this point in the history
  • Loading branch information
@nand2mario
nand2mario committed Mar 30, 2024
1 parent bff32fa commit fb855c5
Show file tree
Hide file tree
Showing 3 changed files with 49 additions and 35 deletions.
17 changes: 9 additions & 8 deletions src/game_data.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,17 +8,17 @@ module GameData (
);

// 24KB+ buffer for ROM
// localparam INES_SIZE = 28688; // 28KB + 16
// initial $readmemh("roms/nes15.hex", INES);
localparam INES_SIZE = 24592; // 24KB + 16
initial $readmemh("roms/helloworld.hex", INES);
localparam INES_SIZE = 28688; // 28KB + 16
initial $readmemh("roms/nes15.hex", INES);
// localparam INES_SIZE = 24592; // 24KB + 16
// initial $readmemh("roms/helloworld.hex", INES);

reg [7:0] INES[INES_SIZE:0];
reg [1:0] state = 0;
reg [$clog2(INES_SIZE)-1:0] addr = 0;
reg out_clk = 0;

reg cnt;
reg [1:0] cnt;

always @(posedge clk) begin
if (reset) begin
Expand All @@ -31,21 +31,22 @@ always @(posedge clk) begin
downloading <= 1;
cnt <= 0;
end else if (state==1) begin
cnt <= ~cnt;
cnt <= cnt + 1;
odata_clk <= 0;
case (cnt)
1'b0: begin
2'd0: begin
// Output one byte to Game_Loader
odata <= INES[addr];
odata_clk <= 1;
end
1'b1: begin
2'd3: begin
if (addr == INES_SIZE-1) begin // done
state <= 2;
downloading <= 0;
end
addr <= addr + 1;
end
default: ;
endcase
end
end
Expand Down
11 changes: 7 additions & 4 deletions src/nestang_top.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -91,6 +91,8 @@ wire blend = 0;
wire bk_save = 0;

// NES signals
reg reset_nes = 1;
reg clkref;
wire [5:0] color;
wire [15:0] sample;
wire [8:0] scanline;
Expand Down Expand Up @@ -291,7 +293,7 @@ end

// From sdram_nes.v or sdram_sim.v
sdram_nes sdram (
.clk(fclk), .clkref(clk), .resetn(sys_resetn), .busy(sdram_busy),
.clk(fclk), .clkref(clkref), .resetn(sys_resetn), .busy(sdram_busy),

.SDRAM_DQ(IO_sdram_dq), .SDRAM_A(O_sdram_addr), .SDRAM_BA(O_sdram_ba),
.SDRAM_nCS(O_sdram_cs_n), .SDRAM_nWE(O_sdram_wen_n), .SDRAM_nRAS(O_sdram_ras_n),
Expand Down Expand Up @@ -327,11 +329,12 @@ GameLoader loader(
assign int_audio = 1;
assign ext_audio = (mapper_flags[7:0] == 19) | (mapper_flags[7:0] == 24) | (mapper_flags[7:0] == 26);

reg reset_nes = 1;
always @(posedge clk) begin
if (~loading && loading_r)
clkref <= ~clkref;
if (~loading && loading_r) begin
reset_nes <= 0;
else if (loading && ~loading_r)
clkref <= 0;
end else if (loading && ~loading_r)
reset_nes <= 1;
end

Expand Down
56 changes: 33 additions & 23 deletions src/verilator/sdram_sim.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,33 +10,33 @@ import configPackage::*;

module sdram_nes
(
inout reg [SDRAM_DATA_WIDTH-1:0] SDRAM_DQ, // 16 bit bidirectional data bus
output [SDRAM_ROW_WIDTH-1:0] SDRAM_A, // 13 bit multiplexed address bus
output reg [SDRAM_DATA_WIDTH/8-1:0] SDRAM_DQM, // two byte masks
output reg [1:0] SDRAM_BA, // two banks
output SDRAM_nCS, // a single chip select
output SDRAM_nWE, // write enable
output SDRAM_nRAS, // row address select
output SDRAM_nCAS, // columns address select
inout reg [SDRAM_DATA_WIDTH-1:0] SDRAM_DQ, // 16 bit bidirectional data bus
output [SDRAM_ROW_WIDTH-1:0] SDRAM_A, // 13 bit multiplexed address bus
output reg [SDRAM_DATA_WIDTH/8-1:0] SDRAM_DQM, // two byte masks
output reg [1:0] SDRAM_BA, // two banks
output SDRAM_nCS, // a single chip select
output SDRAM_nWE, // write enable
output SDRAM_nRAS, // row address select
output SDRAM_nCAS, // columns address select
output SDRAM_CKE,

// cpu/chipset interface
input clk, // main clock @ 21.477Mhz
input resetn,
// cpu/chipset interface
input clk, // main clock @ 21.477Mhz
input resetn,
input clkref,
output reg busy,

input [21:0] addrA, // 22 bit byte address, bank 0/1
input weA, // ppu requests write
input [7:0] dinA, // data input from cpu
input oeA, // ppu requests data
output reg [7:0] doutA, // data output to cpu
input [21:0] addrA, // 22 bit byte address, bank 0/1
input weA, // ppu requests write
input [7:0] dinA, // data input from cpu
input oeA, // ppu requests data
output reg [7:0] doutA, // data output to cpu

input [21:0] addrB, // 21 bit byte address, also bank 0/1
input weB, // cpu requests write
input [7:0] dinB, // data input from ppu
input oeB, // cpu requests data
output reg [7:0] doutB, // data output to ppu
input [21:0] addrB, // 21 bit byte address, also bank 0/1
input weB, // cpu requests write
input [7:0] dinB, // data input from ppu
input oeB, // cpu requests data
output reg [7:0] doutB, // data output to ppu

// RISC-V softcore
input [20:1] rv_addr, // 2MB RV memory space, bank 2
Expand Down Expand Up @@ -77,6 +77,10 @@ reg [7:0] doutA_pre, doutB_pre;
reg [15:0] rv_dout_pre;
reg rv_req_new;

reg oeA_d, oeB_d, weA_d, weB_d;
wire reqA = (~oeA_d & oeA) || (~weA_d & weA);
wire reqB = (~oeB_d & oeB) || (~weB_d & weB);

always @(posedge clk) begin
reg rv_req_new_t;
rv_req_new_t = rv_req ^ rv_req_r;
Expand All @@ -90,15 +94,21 @@ always @(posedge clk) begin

// RAS
if (cycle == 1'b1) begin
if (oeB || weB) begin // CPU

oeA_d <= oeA_d & oeA; weA_d <= weA_d & weA;
oeB_d <= oeB_d & oeB; weB_d <= weB_d & weB;

if (reqB) begin // CPU
oeB_d <= oeB; weB_d <= weB;
port[0] <= PORT_B;
{we_latch[0], oe_latch[0]} <= {weB, oeB};
if (weB) begin
mem_cpu[addrB] <= dinB;
// $fdisplay(32'h80000002, "[%06x] <= %02x", addrB, dinB);
end else
doutB_pre <= mem_cpu[addrB];
end else if (oeA || weA) begin // PPU
end else if (reqA) begin // PPU
oeA_d <= oeA; weA_d <= weA;
port[0] <= PORT_A;
{we_latch[0], oe_latch[0]} <= {weA, oeA};
if (weA) begin
Expand Down

0 comments on commit fb855c5

Please sign in to comment.