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fix iosys rom loading
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@nand2mario
nand2mario committed Apr 1, 2024
1 parent dbd0187 commit fe53b07
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Showing 4 changed files with 85 additions and 97 deletions.
2 changes: 1 addition & 1 deletion nestang_primer25k.gprj
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Original file line number Diff line number Diff line change
Expand Up @@ -65,6 +65,6 @@
<File path="src/tang_primer_25k/nestang.cst" type="file.cst" enable="1"/>
<File path="src/tang_nano_20k/nestang.sdc" type="file.sdc" enable="0"/>
<File path="src/tang_primer_25k/nestang.sdc" type="file.sdc" enable="1"/>
<File path="src/nes.gao" type="file.gao" enable="0"/>
<File path="src/nes.gao" type="file.gao" enable="1"/>
</FileList>
</Project>
17 changes: 10 additions & 7 deletions src/iosys/iosys.v
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Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ module iosys #(
(
input clk, // SNES mclk
input hclk, // hdmi clock
// input clkref, // 1/2 of mclk, for sdram access synchronization
// input clkref, // 1/2 of clk
input resetn,

// OSD display interface
Expand Down Expand Up @@ -273,24 +273,27 @@ simplespimaster simplespi (
.reg_wait(simplespimaster_reg_wait)
);

// ROM loading I/O
reg [1:0] rom_cnt;
// ROM loading I/O. 2 cycles for a byte and 2 cycles idles.
reg [3:0] rom_cnt;
reg [31:0] rom_do_buf;
assign rom_do = rom_do_buf[7:0];
always @(posedge clk) begin
rom_do_valid <= 0;
if (rom_cnt != 0)
rom_cnt <= rom_cnt - 2'd1;
// data register
if (romload_reg_data_sel && mem_wstrb) begin
rom_do_buf <= mem_wdata;
rom_cnt <= 2'd3;
rom_cnt <= 4'd15;
rom_do_valid <= 1;
end
if (rom_cnt != 2'd0) begin // output remaining rom_do
if (rom_cnt[1:0] == 2'd3)
rom_do_valid <= 0;
if (rom_cnt[1:0] == 2'd0 && rom_cnt[3:2] != 0) begin
rom_do_buf[23:0] <= rom_do_buf[31:8];
rom_cnt <= rom_cnt - 2'd1;
rom_do_valid <= 1;
end
end

always @(posedge clk) begin
if (romload_reg_ctrl_sel && mem_wstrb) begin
// control register
Expand Down
154 changes: 73 additions & 81 deletions src/nes.gao
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Original file line number Diff line number Diff line change
Expand Up @@ -2,94 +2,86 @@
<GAO_CONFIG>
<Version>3.0</Version>
<Mode>Standard</Mode>
<AoCore index="0" sample_clock="clk" trig_type="0" storage_depth="2048" window_num="1" capture_amount="1024" trigger_pos="0" module_name="NES_Tang20k" force_trigger_by_falling_edge="false">
<AoCore index="0" sample_clock="clk" trig_type="0" storage_depth="2048" window_num="1" capture_amount="2048" implementation="0" trigger_pos="0" module_name="nestang_top" force_trigger_by_falling_edge="false">
<SignalList>
<Bus name="nes_ce[3:0]">
<Signal>nes_ce[3]</Signal>
<Signal>nes_ce[2]</Signal>
<Signal>nes_ce[1]</Signal>
<Signal>nes_ce[0]</Signal>
<Signal capture_enable="true">loading</Signal>
<Bus capture_enable="true" name="loader_addr_mem[21:0]">
<Signal>loader_addr_mem[21]</Signal>
<Signal>loader_addr_mem[20]</Signal>
<Signal>loader_addr_mem[19]</Signal>
<Signal>loader_addr_mem[18]</Signal>
<Signal>loader_addr_mem[17]</Signal>
<Signal>loader_addr_mem[16]</Signal>
<Signal>loader_addr_mem[15]</Signal>
<Signal>loader_addr_mem[14]</Signal>
<Signal>loader_addr_mem[13]</Signal>
<Signal>loader_addr_mem[12]</Signal>
<Signal>loader_addr_mem[11]</Signal>
<Signal>loader_addr_mem[10]</Signal>
<Signal>loader_addr_mem[9]</Signal>
<Signal>loader_addr_mem[8]</Signal>
<Signal>loader_addr_mem[7]</Signal>
<Signal>loader_addr_mem[6]</Signal>
<Signal>loader_addr_mem[5]</Signal>
<Signal>loader_addr_mem[4]</Signal>
<Signal>loader_addr_mem[3]</Signal>
<Signal>loader_addr_mem[2]</Signal>
<Signal>loader_addr_mem[1]</Signal>
<Signal>loader_addr_mem[0]</Signal>
</Bus>
<Signal>memory/MemBusy</Signal>
<Signal>memory/MemRD</Signal>
<Signal>memory/MemWR</Signal>
<Signal>memory/MemRefresh</Signal>
<Bus name="memory/MemAddr[15:0]">
<Signal>memory/MemAddr[15]</Signal>
<Signal>memory/MemAddr[14]</Signal>
<Signal>memory/MemAddr[13]</Signal>
<Signal>memory/MemAddr[12]</Signal>
<Signal>memory/MemAddr[11]</Signal>
<Signal>memory/MemAddr[10]</Signal>
<Signal>memory/MemAddr[9]</Signal>
<Signal>memory/MemAddr[8]</Signal>
<Signal>memory/MemAddr[7]</Signal>
<Signal>memory/MemAddr[6]</Signal>
<Signal>memory/MemAddr[5]</Signal>
<Signal>memory/MemAddr[4]</Signal>
<Signal>memory/MemAddr[3]</Signal>
<Signal>memory/MemAddr[2]</Signal>
<Signal>memory/MemAddr[1]</Signal>
<Signal>memory/MemAddr[0]</Signal>
<Signal capture_enable="true">loader_write_mem</Signal>
<Bus capture_enable="true" name="loader_write_data_mem[7:0]">
<Signal>loader_write_data_mem[7]</Signal>
<Signal>loader_write_data_mem[6]</Signal>
<Signal>loader_write_data_mem[5]</Signal>
<Signal>loader_write_data_mem[4]</Signal>
<Signal>loader_write_data_mem[3]</Signal>
<Signal>loader_write_data_mem[2]</Signal>
<Signal>loader_write_data_mem[1]</Signal>
<Signal>loader_write_data_mem[0]</Signal>
</Bus>
<Signal>memory/MemDataReady</Signal>
<Bus name="memory/MemDout[15:0]">
<Signal>memory/MemDout[15]</Signal>
<Signal>memory/MemDout[14]</Signal>
<Signal>memory/MemDout[13]</Signal>
<Signal>memory/MemDout[12]</Signal>
<Signal>memory/MemDout[11]</Signal>
<Signal>memory/MemDout[10]</Signal>
<Signal>memory/MemDout[9]</Signal>
<Signal>memory/MemDout[8]</Signal>
<Signal>memory/MemDout[7]</Signal>
<Signal>memory/MemDout[6]</Signal>
<Signal>memory/MemDout[5]</Signal>
<Signal>memory/MemDout[4]</Signal>
<Signal>memory/MemDout[3]</Signal>
<Signal>memory/MemDout[2]</Signal>
<Signal>memory/MemDout[1]</Signal>
<Signal>memory/MemDout[0]</Signal>
<Bus capture_enable="true" name="loader_do[7:0]">
<Signal>loader_do[7]</Signal>
<Signal>loader_do[6]</Signal>
<Signal>loader_do[5]</Signal>
<Signal>loader_do[4]</Signal>
<Signal>loader_do[3]</Signal>
<Signal>loader_do[2]</Signal>
<Signal>loader_do[1]</Signal>
<Signal>loader_do[0]</Signal>
</Bus>
<Bus name="memory/MemDin[15:8]">
<Signal>memory/MemDin[15]</Signal>
<Signal>memory/MemDin[14]</Signal>
<Signal>memory/MemDin[13]</Signal>
<Signal>memory/MemDin[12]</Signal>
<Signal>memory/MemDin[11]</Signal>
<Signal>memory/MemDin[10]</Signal>
<Signal>memory/MemDin[9]</Signal>
<Signal>memory/MemDin[8]</Signal>
<Signal capture_enable="true">loader_do_valid</Signal>
<Bus capture_enable="true" name="iosys/rom_do_buf[31:8]">
<Signal>iosys/rom_do_buf[31]</Signal>
<Signal>iosys/rom_do_buf[30]</Signal>
<Signal>iosys/rom_do_buf[29]</Signal>
<Signal>iosys/rom_do_buf[28]</Signal>
<Signal>iosys/rom_do_buf[27]</Signal>
<Signal>iosys/rom_do_buf[26]</Signal>
<Signal>iosys/rom_do_buf[25]</Signal>
<Signal>iosys/rom_do_buf[24]</Signal>
<Signal>iosys/rom_do_buf[23]</Signal>
<Signal>iosys/rom_do_buf[22]</Signal>
<Signal>iosys/rom_do_buf[21]</Signal>
<Signal>iosys/rom_do_buf[20]</Signal>
<Signal>iosys/rom_do_buf[19]</Signal>
<Signal>iosys/rom_do_buf[18]</Signal>
<Signal>iosys/rom_do_buf[17]</Signal>
<Signal>iosys/rom_do_buf[16]</Signal>
<Signal>iosys/rom_do_buf[15]</Signal>
<Signal>iosys/rom_do_buf[14]</Signal>
<Signal>iosys/rom_do_buf[13]</Signal>
<Signal>iosys/rom_do_buf[12]</Signal>
<Signal>iosys/rom_do_buf[11]</Signal>
<Signal>iosys/rom_do_buf[10]</Signal>
<Signal>iosys/rom_do_buf[9]</Signal>
<Signal>iosys/rom_do_buf[8]</Signal>
</Bus>
</SignalList>
<Triggers>
<Trigger index="0">
<SignalList>
<Signal>memory/MemRD</Signal>
<Bus restorename="memory/MemAddr[21:0]">
<Signal>memory/MemAddr[21]</Signal>
<Signal>memory/MemAddr[20]</Signal>
<Signal>memory/MemAddr[19]</Signal>
<Signal>memory/MemAddr[18]</Signal>
<Signal>memory/MemAddr[17]</Signal>
<Signal>memory/MemAddr[16]</Signal>
<Signal>memory/MemAddr[15]</Signal>
<Signal>memory/MemAddr[14]</Signal>
<Signal>memory/MemAddr[13]</Signal>
<Signal>memory/MemAddr[12]</Signal>
<Signal>memory/MemAddr[11]</Signal>
<Signal>memory/MemAddr[10]</Signal>
<Signal>memory/MemAddr[9]</Signal>
<Signal>memory/MemAddr[8]</Signal>
<Signal>memory/MemAddr[7]</Signal>
<Signal>memory/MemAddr[6]</Signal>
<Signal>memory/MemAddr[5]</Signal>
<Signal>memory/MemAddr[4]</Signal>
<Signal>memory/MemAddr[3]</Signal>
<Signal>memory/MemAddr[2]</Signal>
<Signal>memory/MemAddr[1]</Signal>
<Signal>memory/MemAddr[0]</Signal>
</Bus>
<Signal>loader_do_valid</Signal>
</SignalList>
</Trigger>
<Trigger index="1"/>
Expand All @@ -109,7 +101,7 @@
<Trigger index="15"/>
</Triggers>
<MatchUnits>
<MatchUnit index="0" enabled="1" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="10000000000000001110000" value1="00000000000000000000000" trigger="0"/>
<MatchUnit index="0" enabled="1" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="1" value1="0" trigger="0"/>
<MatchUnit index="1" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="1" value0="001111" value1="000000" trigger="1"/>
<MatchUnit index="2" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
<MatchUnit index="3" enabled="0" match_type="0" counter_enable="0" counter_width="2" counter="2" countinuous="0" func="0" value0="" value1=""/>
Expand All @@ -130,5 +122,5 @@
<Expression>M0</Expression>
</Expressions>
</AoCore>
<GAO_ID>0010011011001111</GAO_ID>
<GAO_ID>1000111000001011</GAO_ID>
</GAO_CONFIG>
9 changes: 1 addition & 8 deletions src/nestang_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -292,13 +292,6 @@ always @(posedge clk) begin
loader_addr_mem <= loader_addr;
loader_write_data_mem <= loader_write_data;
end

// signal write in the PPU memory phase
// if(nes_ce == 3) begin
// loader_write_mem <= loader_write_triggered;
// if(loader_write_triggered)
// loader_write_triggered <= 1'b0;
// end
end

// From sdram_nes.v or sdram_sim.v
Expand All @@ -325,7 +318,7 @@ sdram_nes sdram (

// ROM parser
GameLoader loader(
.clk(clk), .reset(~sys_resetn), .downloading(loading),
.clk(clk), .reset(~sys_resetn | loader_reset), .downloading(loading),
.filetype({4'b0000, type_nsf, type_fds, type_nes, type_bios}),
.is_bios(is_bios), .invert_mirroring(1'b0),
.indata(loader_do), .indata_clk(loader_do_valid),
Expand Down

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