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1. ROUTER-1-3 ROUTER-1-3 Public

   verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL

   SystemVerilog 12 7

2. ROUTER-DESIGN--RTL ROUTER-DESIGN--RTL Public

   Designing of basic router 1*3

   Verilog 2 1

3. UART16550 UART16550 Public

   verification of UART16550 using UVM testbench

   SystemVerilog 1