Fix cell path in designflow.technos for lsxlib.

lip6 · Feb 12, 2024 · abb8dcf · abb8dcf
1 parent 1388da8
commit abb8dcf
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Showing 2 changed files with 9 additions and 8 deletions.
diff --git a/crlcore/python/technos/symbolic/lcmos/alliance.py b/crlcore/python/technos/symbolic/lcmos/alliance.py
@@ -46,11 +46,11 @@
 env.setRegister       ( 'sff.*' )
 
 env.setWORKING_LIBRARY( '.' )
-env.addSYSTEM_LIBRARY ( library=cellsTop+'/sxlib'   , mode=Environment.Append )
-env.addSYSTEM_LIBRARY ( library=cellsTop+'/dp_sxlib', mode=Environment.Append )
-env.addSYSTEM_LIBRARY ( library=cellsTop+'/ramlib'  , mode=Environment.Append )
-env.addSYSTEM_LIBRARY ( library=cellsTop+'/romlib'  , mode=Environment.Append )
-env.addSYSTEM_LIBRARY ( library=cellsTop+'/rflib'   , mode=Environment.Append )
-env.addSYSTEM_LIBRARY ( library=cellsTop+'/rf2lib'  , mode=Environment.Append )
-env.addSYSTEM_LIBRARY ( library=cellsTop+'/pxlib'   , mode=Environment.Append )
-env.addSYSTEM_LIBRARY ( library=cellsTop+'/padlib'  , mode=Environment.Append )
+#env.addSYSTEM_LIBRARY ( library=cellsTop+'/sxlib'   , mode=Environment.Append )
+#env.addSYSTEM_LIBRARY ( library=cellsTop+'/dp_sxlib', mode=Environment.Append )
+#env.addSYSTEM_LIBRARY ( library=cellsTop+'/ramlib'  , mode=Environment.Append )
+#env.addSYSTEM_LIBRARY ( library=cellsTop+'/romlib'  , mode=Environment.Append )
+#env.addSYSTEM_LIBRARY ( library=cellsTop+'/rflib'   , mode=Environment.Append )
+#env.addSYSTEM_LIBRARY ( library=cellsTop+'/rf2lib'  , mode=Environment.Append )
+#env.addSYSTEM_LIBRARY ( library=cellsTop+'/pxlib'   , mode=Environment.Append )
+#env.addSYSTEM_LIBRARY ( library=cellsTop+'/padlib'  , mode=Environment.Append )
diff --git a/cumulus/src/designflow/technos.py b/cumulus/src/designflow/technos.py
@@ -112,6 +112,7 @@ def setupLCMOS ( checkToolkit=None ):
         af  = CRL.AllianceFramework.get()
         env = af.getEnvironment()
         env.setCLOCK( '^ck$|m_clock|^clk$' )
+        env.addSYSTEM_LIBRARY ( library=(Where.checkToolkit / 'cells' / 'lsxlib').as_posix(), mode=CRL.Environment.Append )
 
     Yosys.setLiberty( Where.checkToolkit / 'cells' / 'lsxlib' / 'lsxlib.lib' )
     ShellEnv.RDS_TECHNO_NAME = (Where.allianceTop / 'etc' / 'cmos.rds').as_posix()