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Rebase analog fixes #110
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Merged
Rebase analog fixes #110
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17bff6a
Add support for MOSIS & AMS350 (c35b4) in designflow.technos.
jpc-lip6 4ff63cf
The karakaze tool (AnalogDesign) was forgotten in the installation.
jpc-lip6 7926084
Intalling the techno files for gf180mcu_c4m from CRL.
jpc-lip6 1b31166
The designflow sv2v, svase & surelog were forgotten in the merges.
jpc-lip6 8aa6565
One more forgotten to install gf180mcu file.
jpc-lip6 118913c
Must setup the Coriolis source directory in regression tests.
jpc-lip6 4ca2809
Create separate rules for meson configure & setup.
jpc-lip6 60bc114
New Rectilinear::getAsBiggestrectangles() method.
jpc-lip6 4146bae
In technos.setupCMOS(), find liberty from ALLIANCE_TOP instead of CEL…
jpc-lip6 e8def68
Slightly clrearer display of C++ exception catched through Python.
jpc-lip6 33e5861
Systematically throw an error in case of faulty contact topology.
jpc-lip6 55678be
Reorganization of the size detection of RoutingPad.
jpc-lip6 845cd30
Implementation of Pin Rectilinear Support
jpc-lip6 af8c71f
Create the first technical log entry.
jpc-lip6 8485f0b
The karakaze tool (AnalogDesign) was forgotten in the installation.
jpc-lip6 95b4577
Make the left menu *not* overlap the page contents.
jpc-lip6 983cf4b
Add all the .rst page dependencies to meson.buil.
jpc-lip6 30861eb
In GF180MCU techno, configuration now support HV or VH topologies.
jpc-lip6 3829a80
In LefParser::_pinStdPostProcess(), improved way to choose H/V.
jpc-lip6 246fa6d
In technos.setupGF180MCU_GF(), provide a flag to select HV or VH.
jpc-lip6 04fde50
Support for offgrid M1 & VH topologies (WIP 1).
jpc-lip6 1a98984
New type of LayerRoutingGauge : LocalOnly, for local interconnect.
jpc-lip6 d4105d8
Do not process the blockages layers in FlattenPower (not needed).
jpc-lip6 65cae59
A DebugSession was left open in Katana::PropagateCagedConstraints().
jpc-lip6 aff70ef
Create a new type of TrakElement : TrackBlockage.
jpc-lip6 b715212
More adjustements for the perpandicular track span & positions.
jpc-lip6 e8d5582
Keep track of the position of the BreakpointWidget.
jpc-lip6 b624c77
Display the "ripup ratio" in Katana::Statistics (NegociateWidow).
jpc-lip6 4db450e
Support saving & restoring positions and settings of graphic windows.
jpc-lip6 5927fe4
In Rectilinear, support for horizontal slicing.
jpc-lip6 c607d43
Support Rectilinear in the two setupPowerRails() (Etesian & Katana).
jpc-lip6 f7a339a
Fix TrackBlockage::_getString() when the is not yet a track (transient).
jpc-lip6 b03c7e3
protectRoutingPads() call moved from ::digitalInit() to ::runGlobalro…
jpc-lip6 bdc035f
Support for offgrid M1 & VH topologies (WIP 2).
jpc-lip6 6d37f7c
Support for offgrid M1 & VH topologies (WIP 3).
jpc-lip6 9f675e8
Ignore Emacs backup files.
jpc-lip6 72a4e80
Fix in oroshi.Stack, PMOS must be in nWell (not pWell).
jpc-lip6 508e572
Seems that when doc only is acivated, we no longer could compile.
jpc-lip6 a8eff15
Fixes in protectRoutingPads().
jpc-lip6 9df0b5c
In selectRpComponent(), do not deflate VIAs in symbolic mode.
jpc-lip6 76322a9
New Rectilinear::getAsBiggestrectangles() method.
jpc-lip6 4287835
Support for offgrid M1 & VH topologies (WIP 1).
jpc-lip6 26d1428
Removing code duplication due to a bad merge in Rectilinear.
jpc-lip6 4d18fc6
Force DoglegDown when slackening and AutoSegment from a Terminal.
jpc-lip6 8f74dc4
In NetBuilderHV, check for up density before moving up a global.
jpc-lip6 aab4c5a
Added isUsable() and getFirstroutingLayer() proxies to Anabatic::Conf…
jpc-lip6 533b102
Export RoutingLayerGauge::isHorizontal() & isVertical() to Python.
jpc-lip6 feff2de
Add a failsafe in case the graphic style index no longer exists.
jpc-lip6 e8ed673
Fix wrong import path.
jpc-lip6 1418f47
Manage layer change for south terminals of a macro.
jpc-lip6 758fe3a
More accurate search for obstacle of the H-Tree sub-branches.
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It's unclear to me what's going on here. Why is depth 1 special?
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Mmm. It means that if either we are at depth 0 (
M1
) or above depth 3 (M3
), we use the specific wire width and perpandicular pitch of those layers. Otherwise (M2
orM3
) we use the default defined wire width and perpandicular. Re-reading that code make me thinks I could do it in a more clear way.There was a problem hiding this comment.
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Maybe at least commenting it, as it's difficult to understand for someone that doesn't know the codebase
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Yes. But, this is typically something I should rewrite and cleanup.