Expanded support for CFUs.

.gitmodules

@@ -1,3 +1,4 @@
-[submodule "litex/data/cpu/vexriscv/verilog/ext/VexRiscv"]
+[submodule "pythondata_cpu_vexriscv/verilog/ext/VexRiscv"]
 	path = pythondata_cpu_vexriscv/verilog/ext/VexRiscv
 	url = https://github.com/SpinalHDL/VexRiscv.git
+	branch = master

pythondata_cpu_vexriscv/verilog/Makefile

@@ -1,6 +1,6 @@
 SRC := ${shell find . -type f -name \*.scala}
 
-all: VexRiscv.v VexRiscv_Debug.v VexRiscv_Lite.v VexRiscv_LiteDebug.v VexRiscv_IMAC.v VexRiscv_IMACDebug.v VexRiscv_Min.v VexRiscv_MinDebug.v VexRiscv_Full.v VexRiscv_FullDebug.v VexRiscv_FullCfu.v VexRiscv_FullCfuDebug.v VexRiscv_Linux.v VexRiscv_LinuxDebug.v VexRiscv_LinuxNoDspFmax.v VexRiscv_Secure.v VexRiscv_SecureDebug.v
+all: VexRiscv.v VexRiscv_Debug.v VexRiscv_Lite.v VexRiscv_LiteDebug.v VexRiscv_IMAC.v VexRiscv_IMACDebug.v VexRiscv_Min.v VexRiscv_MinDebug.v VexRiscv_Full.v VexRiscv_FullDebug.v VexRiscv_FullCfu.v VexRiscv_FullCfuDebug.v VexRiscv_Linux.v VexRiscv_LinuxDebug.v VexRiscv_LinuxNoDspFmax.v VexRiscv_Secure.v VexRiscv_SecureDebug.v VexRiscv_SlimCfu.v VexRiscv_SlimCfuDebug.v VexRiscv_Fomu.v VexRiscv_FomuCfu.v VexRiscv_PerfCfu.v VexRiscv_PerfCfuDebug.v VexRiscv_SlimPerfCfu.v VexRiscv_SlimPerfCfuDebug.v
 
 VexRiscv.v: $(SRC)
 	sbt compile "runMain vexriscv.GenCoreDefault"
@@ -26,17 +26,44 @@ VexRiscv_Min.v: $(SRC)
 VexRiscv_MinDebug.v: $(SRC)
 	sbt compile "runMain vexriscv.GenCoreDefault -d --iCacheSize 0 --dCacheSize 0 --mulDiv false --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --outputFile VexRiscv_MinDebug"
 
+VexRiscv_Fomu.v: $(SRC)
+	sbt compile "runMain vexriscv.GenCoreDefault --safe false --iCacheSize 2048 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift true --singleCycleMulDiv true --bypass false --prediction none --hardwareDiv false --outputFile VexRiscv_Fomu"
+
+VexRiscv_FomuCfu.v: $(SRC)
+	sbt compile "runMain vexriscv.GenCoreDefault --safe false --cfu true --iCacheSize 2048 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift true --singleCycleMulDiv true --bypass false --prediction none --hardwareDiv false --outputFile VexRiscv_FomuCfu"
+
 VexRiscv_Full.v: $(SRC)
 	sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all --outputFile VexRiscv_Full"
 
 VexRiscv_FullDebug.v: $(SRC)
 	sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all -d --outputFile VexRiscv_FullDebug"
 
 VexRiscv_FullCfu.v: $(SRC)
-	sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all --cfu true --outputFile VexRiscv_FullCfu"
+	sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all --cfu true --outputFile VexRiscv_FullCfu"
 
 VexRiscv_FullCfuDebug.v: $(SRC)
-	sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all --cfu true -d --outputFile VexRiscv_FullCfuDebug"
+	sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all -d --cfu true --outputFile VexRiscv_FullCfuDebug"
+
+VexRiscv_PerfCfu.v: $(SRC)
+	sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all --cfu true --perfCSRs 8 --outputFile VexRiscv_PerfCfu"
+
+VexRiscv_PerfCfuDebug.v: $(SRC)
+	sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all -d --cfu true --perfCSRs 8 --outputFile VexRiscv_PerfCfuDebug"
+
+VexRiscv_Slim.v: $(SRC)
+	sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 4096 --iCacheSize 2048 --csrPluginConfig all --outputFile VexRiscv_Slim"
+
+VexRiscv_SlimCfu.v: $(SRC)
+	sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 4096 --iCacheSize 2048 --csrPluginConfig all --cfu true --outputFile VexRiscv_SlimCfu"
+
+VexRiscv_SlimCfuDebug.v: $(SRC)
+	sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 4096 --iCacheSize 2048 --csrPluginConfig all -d --cfu true --outputFile VexRiscv_SlimCfuDebug"
+
+VexRiscv_SlimPerfCfu.v: $(SRC)
+	sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 4096 --iCacheSize 2048 --csrPluginConfig all --cfu true --perfCSRs 8 --outputFile VexRiscv_SlimPerfCfu"
+
+VexRiscv_SlimPerfCfuDebug.v: $(SRC)
+	sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 4096 --iCacheSize 2048 --csrPluginConfig all -d --cfu true --perfCSRs 8 --outputFile VexRiscv_SlimPerfCfuDebug"
 
 VexRiscv_Linux.v: $(SRC)
 	sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig linux-minimal --outputFile VexRiscv_Linux"

pythondata_cpu_vexriscv/verilog/README.md

@@ -17,6 +17,16 @@ src/main/scala/vexriscv GenCoreDefault.scala
 - Available in normal an -Debug, with the Debug bus exposed
 
 
+## Changes in `tcal-x`'s fork
+
+- Now submodule ext/VexRiscv uses tip of `dev` branch
+- Added ext/SpinalHDL submodule, also `dev` branch
+- Modified `build.sbt` to bring up to date with current `dev` VexRiscv
+- Modified `src/main/scala/vexriscv/GenCoreDefault.scala` to add a `--cfu` option, to add the CFU interface
+- Added `VexRiscv_FullCfu.v` and `VexRiscv_FullCfuDebug.v` (and yamls), and updated `Makefile` to build them
+- I did **not** rebuild the other .v/.yaml files
+
+
 ## Requirements
 
 - Java 8

pythondata_cpu_vexriscv/verilog/VexRiscv.v

@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.6.0    git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3
 // Component : VexRiscv
-// Git hash  : 6276bf628be9d0a58c0284dca83137b71ef29098
+// Git hash  : 593e180abf5ba39e7fa33d4f371646453f84496a
 
 
 `define EnvCtrlEnum_binary_sequential_type [1:0]

pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v

@@ -1,6 +1,6 @@
 // Generator : SpinalHDL v1.6.0    git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3
 // Component : VexRiscv
-// Git hash  : 6276bf628be9d0a58c0284dca83137b71ef29098
+// Git hash  : 593e180abf5ba39e7fa33d4f371646453f84496a
 
 
 `define EnvCtrlEnum_binary_sequential_type [1:0]