Update (2024.04.26)

33160: LA port of 8261837: SIGSEGV in ciVirtualCallTypeData::translate_from

src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp

@@ -3013,7 +3013,10 @@ void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
   __ verify_oop(obj);
 
   if (tmp != obj) {
+    assert_different_registers(obj, tmp, SCR1, SCR2, mdo_addr.base(), mdo_addr.index());
     __ move(tmp, obj);
+  } else {
+    assert_different_registers(obj, SCR1, SCR2, mdo_addr.base(), mdo_addr.index());
   }
   if (do_null) {
     __ bnez(tmp, update);
@@ -3072,10 +3075,11 @@ void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
           __ beqz(SCR2, none);
           __ li(SCR1, (u1)TypeEntries::null_seen);
           __ beq(SCR2, SCR1, none);
-          // There is a chance that the checks above (re-reading profiling
-          // data from memory) fail if another thread has just set the
+          // There is a chance that the checks above
+          // fail if another thread has just set the
           // profiling to this obj's klass
           membar_acquire();
+          __ XOR(tmp, tmp, SCR2); // get back original value before XOR
           __ ld_ptr(SCR2, mdo_addr);
           __ XOR(tmp, tmp, SCR2);
           assert(TypeEntries::type_klass_mask == -4, "must be");
@@ -3102,6 +3106,11 @@ void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
         __ bind(none);
         // first time here. Set profile type.
         __ st_ptr(tmp, mdo_addr);
+#ifdef ASSERT
+        assert(TypeEntries::type_mask == -2, "must be");
+        __ bstrpick_d(tmp, tmp, 63, 1);
+        __ verify_klass_ptr(tmp);
+#endif
       }
     } else {
       // There's a single possible klass at this profile point
@@ -3135,6 +3144,11 @@ void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
 #endif
         // first time here. Set profile type.
         __ st_ptr(tmp, mdo_addr);
+#ifdef ASSERT
+        assert(TypeEntries::type_mask == -2, "must be");
+        __ bstrpick_d(tmp, tmp, 63, 1);
+        __ verify_klass_ptr(tmp);
+#endif
       } else {
         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");

src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp

@@ -1642,6 +1642,7 @@ void InterpreterMacroAssembler::narrow(Register result) {
 
 
 void InterpreterMacroAssembler::profile_obj_type(Register obj, const Address& mdo_addr) {
+  assert_different_registers(obj, AT, T5, mdo_addr.base(), mdo_addr.index());
   Label update, next, none;
 
   verify_oop(obj);
@@ -1680,25 +1681,21 @@ void InterpreterMacroAssembler::profile_obj_type(Register obj, const Address& md
   xorr(obj, obj, AT);
 
   assert(TypeEntries::type_klass_mask == -4, "must be");
-  bstrpick_d(AT, obj, 63, 2);
-  beqz(AT, next);
+  bstrpick_d(T5, obj, 63, 2);
+  beqz(T5, next);
 
-  andi(AT, obj, TypeEntries::type_unknown);
-  bnez(AT, next);
+  andi(T5, obj, TypeEntries::type_unknown);
+  bnez(T5, next);
 
-  if (mdo_addr.index() == noreg) {
-    ld_d(AT, mdo_addr);
-  } else {
-    ld_d(AT, T0, mdo_addr.disp());
-  }
   beqz(AT, none);
 
-  addi_d(AT, AT, -(TypeEntries::null_seen));
-  beqz(AT, none);
+  addi_d(T5, AT, -(TypeEntries::null_seen));
+  beqz(T5, none);
 
-  // There is a chance that the checks above (re-reading profiling
-  // data from memory) fail if another thread has just set the
+  // There is a chance that the checks above
+  // fail if another thread has just set the
   // profiling to this obj's klass
+  xorr(obj, obj, AT); // get back original value before XOR
   if (mdo_addr.index() == noreg) {
     ld_d(AT, mdo_addr);
   } else {
@@ -1730,6 +1727,11 @@ void InterpreterMacroAssembler::profile_obj_type(Register obj, const Address& md
   } else {
     st_d(obj, T0, mdo_addr.disp());
   }
+#ifdef ASSERT
+  assert(TypeEntries::type_mask == -2, "must be");
+  bstrpick_d(obj, obj, 63, 1);
+  verify_klass_ptr(obj);
+#endif
 
   bind(next);
   if (mdo_addr.index() != noreg) {