[rtl] Fix counter reset value on FPGA #243
Triggered via pull request
November 28, 2024 06:55
nasahlpa
Status
Success
Total duration
11m 23s
Artifacts
–
ci.yml
on: pull_request
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11m 13s
Annotations
10 errors
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Run quality checks (Lint and DV)
The RISC-V compliance test suite failed for rv32i
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Run quality checks (Lint and DV)
Expected failure for rv32i, see lowrisc/ibex#100 more more information.
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Run quality checks (Lint and DV)
The RISC-V compliance test suite failed for rv32i
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Run quality checks (Lint and DV)
Expected failure for rv32i, see lowrisc/ibex#100 more more information.
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Run quality checks (Lint and DV)
The RISC-V compliance test suite failed for rv32i
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Run quality checks (Lint and DV)
Expected failure for rv32i, see lowrisc/ibex#100 more more information.
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Run quality checks (Lint and DV)
The RISC-V compliance test suite failed for rv32i
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Run quality checks (Lint and DV)
Expected failure for rv32i, see lowrisc/ibex#100 more more information.
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Run quality checks (Lint and DV)
The RISC-V compliance test suite failed for rv32i
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Run quality checks (Lint and DV)
Expected failure for rv32i, see lowrisc/ibex#100 more more information.
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