Formal cleanup #272
Annotations
2 errors and 10 warnings
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reviewdog: Too many results (annotations) in diff.
You may miss some annotations due to GitHub limitation for annotation created by logging command.
Please check GitHub Actions log console to see all results.
Limitation:
- 10 warning annotations and 10 error annotations per step
- 50 annotations per job (sum of annotations from all the steps)
- 50 annotations per run (separate from the job annotations, these annotations aren't created by users)
Source: https://github.community/t5/GitHub-Actions/Maximum-number-of-annotations-that-can-be-created-using-GitHub/m-p/39085
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Run Verible linter action
Process completed with exit code 1.
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Run Verible linter action:
dv/formal/check/peek/follower.sv#L52
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]" location:{path:"./dv/formal/check/peek/follower.sv" range:{start:{line:52 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Run Verible linter action:
dv/formal/check/top.sv#L127
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 131 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 131 [Style: line-length] [line-length]" location:{path:"./dv/formal/check/top.sv" range:{start:{line:127 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Run Verible linter action:
dv/formal/check/top.sv#L172
[verible-verilog-lint] reported by reviewdog 🐶
Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]
Raw Output:
message:"Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]" location:{path:"./dv/formal/check/top.sv" range:{start:{line:172 column:23}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Run Verible linter action:
dv/formal/check/top.sv#L265
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]" location:{path:"./dv/formal/check/top.sv" range:{start:{line:265 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Run Verible linter action:
dv/formal/check/top.sv#L268
[verible-verilog-lint] reported by reviewdog 🐶
Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]
Raw Output:
message:"Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]" location:{path:"./dv/formal/check/top.sv" range:{start:{line:268 column:29}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Run Verible linter action:
dv/formal/check/top.sv#L289
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]" location:{path:"./dv/formal/check/top.sv" range:{start:{line:289 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Run Verible linter action:
dv/formal/check/top.sv#L329
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 118 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 118 [Style: line-length] [line-length]" location:{path:"./dv/formal/check/top.sv" range:{start:{line:329 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Run Verible linter action:
dv/formal/check/top.sv#L389
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]" location:{path:"./dv/formal/check/top.sv" range:{start:{line:389 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Run Verible linter action:
dv/formal/check/top.sv#L392
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]" location:{path:"./dv/formal/check/top.sv" range:{start:{line:392 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Run Verible linter action:
dv/formal/spec/spec_api.sv#L102
[verible-verilog-lint] reported by reviewdog 🐶
Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]
Raw Output:
message:"Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]" location:{path:"./dv/formal/spec/spec_api.sv" range:{start:{line:102 column:20}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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