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[dv,py] Tweak ISS linker arg construction for Xcelium #2209

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hcallahan-lowrisc
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The previous code here was a bit too hacky, so implement a solution that directly follows the suggestion in the Cadence support article. An example was also added to make it clear what this transformation is achieving.

Additionally, cleanup some of the other code in the module, renaming for clarity and adding comments. Move some variable declarations around to be closer to their use. Add some more typehints.

Fixes #2205

@hcallahan-lowrisc hcallahan-lowrisc added the Component:DV Design verification (DV) or testing issue label Aug 26, 2024
@hcallahan-lowrisc hcallahan-lowrisc force-pushed the core_ibex_dv_xcelium_iss_flags branch from 4e23e1a to cf0c359 Compare August 26, 2024 13:37
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This drops the

dv/uvm/core_ibex/scripts/compile_tb.py Outdated Show resolved Hide resolved
@hcallahan-lowrisc hcallahan-lowrisc force-pushed the core_ibex_dv_xcelium_iss_flags branch from cf0c359 to 96aef9e Compare October 1, 2024 12:25
The previous code here was a bit too hacky, so implement a solution that
directly follows the suggestion in the Cadence support article.
An example was also added to make it clear what this transformation is
achieving.

Add some more typehints, and cleanup names.

Signed-off-by: Harry Callahan <[email protected]>
Add comments, and move some variable declarations around to be closer to their use.

Signed-off-by: Harry Callahan <[email protected]>
@hcallahan-lowrisc hcallahan-lowrisc force-pushed the core_ibex_dv_xcelium_iss_flags branch from 96aef9e to c9660e5 Compare October 1, 2024 13:58
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Looks sensible to me!

@hcallahan-lowrisc
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Thanks!

@hcallahan-lowrisc hcallahan-lowrisc added this pull request to the merge queue Oct 1, 2024
Merged via the queue into lowRISC:master with commit fb49826 Oct 1, 2024
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@hcallahan-lowrisc hcallahan-lowrisc deleted the core_ibex_dv_xcelium_iss_flags branch October 2, 2024 10:05
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Compile_tb.py generate options not recogised by xrun
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