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GPIO straps verif #25868
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GPIO straps verif #25868
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I think this PR still requires some changes.
`DV_CHECK_MEMBER_RANDOMIZE_WITH_FATAL(delay, delay >= 1;) | ||
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// Trigger the snapshot of gpio_i to be stored in the straps registers | ||
cfg.straps_vif_inst.strap_en = 'b1; |
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Nit: all these 'b
are useless for single bit (IMO)
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Thanks for dropping that. Honestly, I think I generally use 1'b1
but I'm happy either way. But I think there's still a bare 'b1
a few lines later. Maybe switch that to 1
too?
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Yes, I can do that
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hw/ip/gpio/data/gpio.hjson
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desc: '''GPIO Input data sampled as straps during cold boot read value | ||
The GPIO input data is sampled after the first one pulse cycle of straps_en input after reset. | ||
''', |
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I realise this isn't your fault but the text here is a bit dubious! How about something like this?
desc: '''
GPIO input data that was sampled as straps as the block came out of reset.
This register depends on the GpioAsHwStrapsEn parameter.
- If the parameter is false then the register reads as zero.
- If the parameter is true then GPIO input data is sampled on the first cycle after reset
where the strap_en_i input is high. That sampled data is stored in this register.
''',
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Much better! Thanks!
hw/ip/gpio/data/gpio_testplan.hjson
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- Set the expected strap_data_in based on the condition if is the first triggered strap_en or not | ||
- Updates the RAL model with the expected strap_data_in and strap_data_in_valid |
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I think this behaviour is in the scoreboard now, so doesn't need describing here?
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very true, I forgot to remove this. And I have included some new comments/steps description.
hw/ip/gpio/data/gpio_testplan.hjson
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- Drives gpio_i input with random values | ||
- Set the expected strap_data_in based on the condition if is the first triggered strap_en or not | ||
- Updates the RAL model with the expected strap_data_in and strap_data_in_valid | ||
- Trigger the strap_en with one clock cycle |
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I'd suggest making this more general: we're only looking at the "posedge" anyway. Maybe something like "set strap_en_i high for at least one clock cycle".
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fixed
hw/ip/gpio/data/gpio_testplan.hjson
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- Updates the RAL model with the expected strap_data_in and strap_data_in_valid | ||
- Trigger the strap_en with one clock cycle | ||
- Read the registers hw_straps_data_in and hw_straps_data_in_valid | ||
- Check the expected behavior in the scoreboard and also on csr checks''' |
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I'd probably make it more explicit that this isn't done in the sequence. Maybe "The data read will be checked by the scoreboard." ?
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true, I will reformulate the phrase.
hw/ip/gpio/dv/env/gpio_scoreboard.sv
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// hw straps_data_in_valid register | ||
bit straps_data_in_valid; | ||
// hw straps_data_in register | ||
bit [NUM_GPIOS-1:0] straps_data_in; |
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I don't think you're actually using either of these fields. You can probably drop them?
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you are right, I included those in the gpio_predict_and_compare() function, because was initial idea that this function it will be used in my case, but after some coding I realise that is not needed, but I forgot to remove it. I should done a proper clean up code, sorry.
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// Interface definition | ||
interface gpio_straps_if ( | ||
inout strap_en_i, // Input signal to enable straps |
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Nit: Stray space before "strap_en_i"
inout strap_en_i, // Input signal to enable straps | ||
input gpio_straps_t sampled_straps_o // Output signal of type gpio_straps_t |
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I think something very strange is going on here. Do these need to be ports at all? I think probably not, and I definitely don't think an input port should have a name that ends in _o
.
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If the interface is used primarily for encapsulation those signals, then you are correct, but in this case I will connect those ports signals to the GPIO module, otherwise I will have compilation issues.
You are right, besides the "input" explicitly in the sampled_straps_o feels weird/confuse, I kept the _o, just to signalise that this signal is a output from the DUT, but I can remove it, that is more reasonable, and put some comments.
logic strap_en; | ||
assign strap_en_i = strap_en; |
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Again, I'm not sure about the way this is using ports. Can't we just have an internal variable called strap_en
and wire that up?
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In this case I am using the gpio_strap_en variable to initialise the strap_en_i with zero after the reset, otherwise I will have spreading X's to the input, so look at the gpio_base_test.sv
hw/ip/gpio/dv/tb/tb.sv
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@@ -24,6 +22,8 @@ module tb; | |||
wire [NUM_GPIOS-1:0] gpio_oe; | |||
wire [NUM_GPIOS-1:0] gpio_intr; | |||
wire [NUM_MAX_INTERRUPTS-1:0] interrupts; | |||
gpio_straps_t sampled_straps; | |||
wire strap_en_i; |
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This name doesn't quite work because the _i
suffix is used for input ports in our style.
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ok, I will fix this =)
hw/ip/gpio/dv/tb/tb.sv
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// TODO: need to test snapshot functionality | ||
.strap_en_i(1'b0), | ||
.sampled_straps_o(), | ||
.strap_en_i(strap_en_i), |
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Following on from the note I left in the interface, I think this could just use straps_if_inst.strap_en
.
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Yes indeed, I would prefer to keep the single signal name instead, makes the code more clean, and the wire makes the "connection" between the interface and the DUT. But let me know if this does not make sense to you =)
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Signed-off-by: Marcelo Carvalho Faleiro de Almeida <[email protected]>
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New sequence to verify the straps feature and some additional description of the behaviour of this feature in the register document.