docs/SoC_Gowin_GW1NSR.md: document describing Gowin SoC tests added #41
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| ## SoC requirements for TPM | ||
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| As previously stated (and described), a TPM candidate must meet the following |
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@macpijan AFAIK we don't have it described in a single place (and consistent way). We could create separate document for that a and link it here and in other places instead of repeating ourselves.
| part is required, it is not possible to use this memory as RAM for the hard CPU. | ||
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| This fact disqualifies Gowin's SoC from the GW1NSR-4C series as a hardware TPM | ||
| module. |
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Why lack of hardware controller would be a problem when we can have an equivalent on FPGA? Can't the FPGA based controller decode cycles coming from AHB and "forward" communication to/from SRAM?
| The project documentation shows that, among others: | ||
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| + BRAM blocks in FPGA fabric are not properly handled | ||
| + PLL clocks are not supported |
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What problems do arise from lack of this functionality?
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Signed-off-by: Maciej Gabryelski [email protected]